SM8750AV
Phase Difference to Voltage Converter
The phase difference to voltage converter circuit
takes the converts the phase difference between the
RDCLK rising edge and the DATA signal to a volt-
age. When START goes LOW, the phase difference
between the first active DATA signal edge, where the
active edge polarity is determined by the serial inter-
face bit POLAR, and the next RDCLK rising edge is
converted to a voltage signal. The converted voltage
signal is output on TVOUT while START is LOW,
and is reset to the VREF2 reference level when
START goes HIGH again.
The START signal must go LOW for a minimum
interval of 1 RDCLK cycle before any DATA signal
edge to be converted, regardless of the number of
DATA signal edges. If the START interval is shorter
than 1 cycle, there is a possibility that the next edge
might be misinterpreted as the conversion object.
START
RDCLK
DATA
Internal charge signal
Internal discharge signal
TVOUT output
Phase difference
START−DATA set up time
VREF2
Conversion voltage
Reset
VREF2
Figure 1. Converter operation timing (POLAR = LOW, DATA leading phase)
START
RDCLK
DATA
Internal charge signal
Internal discharge signal
TVOUT output
Phase difference
START−DATA set up time
VREF2
Conversion voltage
Reset
VREF2
Figure 2. Converter operation timing (POLAR = LOW, DATA lagging phase)
NIPPON PRECISION CIRCUITS—7