SM8750AV Просмотр технического описания (PDF) - Nippon Precision Circuits

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SM8750AV

Data Jitter Measurement IC

Nippon Precision Circuits  

SM8750AV

Phase Difference to Voltage Converter Characteristics

VDD = 5V ± 5%, GND = 0V, Ta = 0 to 70°C

Parameter

Condition

RDCLK input frequency

Phase difference to voltage converter

coefficient 1

Phase difference to voltage converter

coefficient 2

Phase difference to voltage converter

coefficient 3

Converter coefficient relative accuracy

Converter coefficient relative accuracy

Output offset voltage

Converter voltage settling time

Converter voltage reset time

Output load regulation

HIGH-level output voltage range

L OW -level output voltage range

Output voltage droop

S TA R T-DATA setup time3

FCG = LOW

FCG = HIGH

Normal operation, FCG = LOW

Converter coefficient measurement mode,

FCG = LOW

Normal operation, FCG = HIGH

Converter coefficient measurement mode,

FCG = HIGH

See note.1

See note.2

After VREF2 reference calibration

Time from measurement object DATA

edge to final set value ± 0.5%

Time from STA R T signal rising edge to

final reset value ± 1mV

IL = 0.5mA

LIMIT pin voltage reference

S TA R T signal rising edge to DATA signal

edge

1. {[(converter coefficient 2) × 2 / (converter coefficient 1)] − 1} × 100

2. {[(converter coefficient 3) × 2 / (converter coefficient 2)] − 1} × 100

3. T = RDCLK cycle time

min

–

–

50

25

25

12.5

–

–

–

–

–

–

+0.15

0.8

–

1T

Auto-adjust Characteristics

VDD = 5V ± 5%, GND = 0V, Ta = 0 to 70°C

Parameter

Condition

min

Maximum DATA edge delay adjust range

–

Minimum DATA edge delay adjust range

–

Maximum RDCLK pulsewidth adjust range

–

FCG = LOW

Minimum RDCLK pulsewidth adjust range

–

Maximum RDCLK pulsewidth adjust range

–

FCG = HIGH

Minimum RDCLK pulsewidth adjust range

–

Auto-adjustment time

After CS = HIGH, until settling

–

RCP voltage

Converter coefficients set

–

HIGH-level RDATA R / R DATAF voltage

Minimum DATA delay

–

L OW -level RDATA R / R DATAF voltage

Maximum DATA delay

–

HIGH-level RDUTY voltage

Minimum RDCLK pulsewidth

–

L OW -level RDUTY voltage

Maximum RDCLK pulsewidth

–

Rating

typ

58.38

29.19

75

37.5

37.5

18.75

–

–

–

–

–

–

–

–

–

–

Rating

typ

29

12.5

15

3

28

4

5

1

1.92

0.69

1.88

0.24

max

70

35

100

50

50

25

±5

±5

±25

0.75

3

20

+0.45

–

1

–

max

–

–

–

–

–

–

8

–

–

–

–

–

Unit

MHz

mV/ns

mV/ns

mV/ns

%

%

mV

µs

µs

mV

V

V

mV/µs

ns

Unit

ns

ns

ns

ns

ns

ns

ms

V

V

V

V

V

NIPPON PRECISION CIRCUITS—4

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