CS4630-CM Просмотр технического описания (PDF) - Cirrus Logic

Номер в каталоге

Компоненты Описание

Список матч

CS4630-CM

CrystalClear™ SoundFusion® PCI Audio Accelerator

Cirrus Logic 

CS4630

4. HOST INTERFACE

The CS4630 host interface is comprised of two sep-

arate interface blocks which are memory mapped

into host address space. The interface blocks can be

located anywhere in the host 32-bit physical ad-

dress space. The interface block locations are de-

fined by the addresses programmed into the two

Base Address Registers in the PCI Configuration

Space. These base addresses are normally set up by

the system’s Plug and Play BIOS. The first inter-

face block (located by Base Address 0) is a 4 kByte

register block containing general purpose configu-

ration, control, and status registers for the device.

The second interface block (located by Base Ad-

dress 1) is a 1 MByte block which maps all of the

internal RAM memories (SP Program RAM, Pa-

rameter RAM, and Sample RAM) into host memo-

ry space. This allows the host to directly peek and

poke RAM locations on the device. The relation-

ship between the Base Address Registers in the

CS4630 PCI Configuration Space and the host

memory map is depicted in Figure 10.

The bus mastering PCI bus interface complies with

the PCI Local Bus Specification (version 2.1).

4.1 PCI bus Transactions

As a target of a PCI bus transaction, the CS4630

supports the Memory Read (from internal registers

or memory), Memory Write (to internal registers or

memory), Configuration Read (from CS4630 con-

figuration registers), Configuration Write (to

CS4630 configuration registers), Memory Read

Multiple (aliased to Memory Read), Memory Read

Line (aliased to Memory Read), the Memory Write

and Invalidate (aliased to Memory Write) transfer

cycles, and I/O Read, I/O Write cycles (for legacy

audio support). The Interrupt Acknowledge, Spe-

cial Cycles, and Dual Address Cycle transactions

are not supported.

As Bus Master, the CS4630 generates the Memory

Read Multiple, Memory Write, I/O Read and I/O

Write transactions. The Memory Read, Configura-

tion Read, Configuration Write, Memory Read

Line, Memory Write and Invalidate, Interrupt Ac-

Device PCI Config. Space

00h Device ID / Vendor ID

04h Status / Command

08h Class Code / Revision

0Ch

Misc. Control

10h Base Address Register 0

14h Base Address Register 1

Direct I/O Registers

(Memory Mapped, 4 kByte)

Direct Memory Interface

(Memory Mapped, 1 MByte)

Figure 10. Host Interface Base Address Registers

DS445PP1

15

Share Link: