CS4630-CM Просмотр технического описания (PDF) - Cirrus Logic

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CS4630-CM

CrystalClear™ SoundFusion® PCI Audio Accelerator

Cirrus Logic 

CS4630

EEPROM TIMING CHARACTERISTICS (TA = 0 to 70 °C, PCIVDD = CRYVDD = 3.3 V; CVDD =

2.5V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V;

Timing reference levels = 1.4 V; PCI clock frequency = 33 MHz; unless otherwise noted (Note 4))

Parameter

Symbol

Min

Max

Units

EECLK Low to EEDAT Data Out Valid

tAA

0

Start Condition Hold Time

tHD:STA

5.0

EECLK Low

tLEECLK

10

EECLK High

tHEECLK

10

Start Condition Setup Time (for a Repeated Start Condition)

tSU:STA

5.0

EEDAT In Hold Time

tHD:DAT

0

EEDAT In Setup Time

tSU:DAT

250

EEDAT/EECLK Rise Time

(Note 19)

tR

-

EEDAT/EECLK Fall Time

tF

-

Stop Condition Setup Time

tSU:STO

5.0

EEDAT Out Hold Time

tDH

0

7.0

µs

-

µs

-

µs

-

µs

-

µs

-

µs

-

ns

1

µs

300

ns

-

µs

-

µs

Notes: 19. Rise time on EEDAT is determined by the capacitance on the EEDAT line with all connected gates and

the required external pull-up resistor. Nominal values based on 4.7k and 22pF.

EECLK

EEDAT (IN)

t SU:STA

EEDAT (OUT)

EEDAT (OUT)

DS445PP1

tF

t HEECLK

t LEECLK

t HD:STA

t AA

t HD:DAT

t DH

t SU:DAT

Figure 6. EEPROM Timing

tR

t SU:STO

11

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