TSL2569 Просмотр технического описания (PDF) - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS

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TSL2569

LIGHT-TO-DIGITAL CONVERTER

TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS 

TSL2568, TSL2569

LIGHT-TO-DIGITAL CONVERTER

TAOS091D − DECEMBER 2008

PRINCIPLES OF OPERATION

Analog-to-Digital Converter

The TSL256x contains two integrating analog-to-digital converters (ADC) that integrate the currents from the

channel 0 and channel 1 photodiodes. Integration of both channels occurs simultaneously, and upon completion

of the conversion cycle the conversion result is transferred to the channel 0 and channel 1 data registers,

respectively. The transfers are double buffered to ensure that invalid data is not read during the transfer. After

the transfer, the device automatically begins the next integration cycle.

Digital Interface

Interface and control of the TSL256x is accomplished through a two-wire serial interface to a set of registers

that provide access to device control functions and output data. The serial interface is compatible with System

Management Bus (SMBus) versions 1.1 and 2.0, and I2C bus Fast-Mode. The TSL256x offers three slave

addresses that are selectable via an external pin (ADDR SEL). The slave address options are shown in Table 1.

Table 1. Slave Address Selection

ADDR SEL TERMINAL LEVEL

GND

Float

VDD

SLAVE ADDRESS

0101001

0111001

1001001

SMB ALERT ADDRESS

0001100

0001100

0001100

NOTE: The Slave and SMB Alert Addresses are 7 bits. Please note the SMBus and I2C protocols on pages 9 through 12. A read/write bit should

be appended to the slave address by the master device to properly communicate with the TSL256X device.

SMBus and I2C Protocols

Each Send and Write protocol is, essentially, a series of bytes. A byte sent to the TSL256x with the most

significant bit (MSB) equal to 1 will be interpreted as a COMMAND byte. The lower four bits of the COMMAND

byte form the register select address (see Table 2), which is used to select the destination for the subsequent

byte(s) received. The TSL256x responds to any Receive Byte requests with the contents of the register

specified by the stored register select address.

The TSL256X implements the following protocols of the SMB 2.0 specification:

D Send Byte Protocol

D Receive Byte Protocol

D Write Byte Protocol

D Write Word Protocol

D Read Word Protocol

D Block Write Protocol

D Block Read Protocol

The TSL256X implements the following protocols of the Philips Semiconductor I2C specification:

D I2C Write Protocol

D I2C Read (Combined Format) Protocol

Copyright E 2008, TAOS Inc.

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