TSL2569 Просмотр технического описания (PDF) - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
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TSL2569 Datasheet PDF : 36 Pages
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TSL2568, TSL2569
LIGHT-TO-DIGITAL CONVERTER
1
7
11
8
1
S Slave Address Wr A Command Code A
8
1
Byte Count = N A
TAOS091D − DECEMBER 2008
8
Data Byte 1
1
A ...
8
Data Byte 2
1
A ...
8
Data Byte N
11
AP
Figure 14. SMBus Block Write or I2C Write Protocols
NOTE: The I2C write protocol does not use the Byte Count packet, and the Master will continue sending Data Bytes until the Master initiates a
Stop condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.
1
7
11
S Slave Address Wr A
8
Command Code
11
7
11
A Sr Slave Address Rd A
8
Byte Count = N
1
A ...
8
1
Data Byte 1
A
8
Data Byte 2
1
A ...
8
Data Byte N
11
AP
1
Figure 15. SMBus Block Read or I2C Read (Combined Format) Protocols
NOTE: The I2C read protocol does not use the Byte Count packet, and the Master will continue receiving Data Bytes until the Master initiates
a Stop Condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.
Register Set
The TSL256x is controlled and monitored by sixteen registers (three are reserved) and a command register
accessed through the serial interface. These registers provide for a variety of control functions and can be read
to determine results of the ADC conversions. The register set is summarized in Table 2.
Table 2. Register Address
ADDRESS
−−
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
RESISTER NAME
COMMAND
CONTROL
TIMING
THRESHLOWLOW
THRESHLOWHIGH
THRESHHIGHLOW
THRESHHIGHHIGH
INTERRUPT
−−
CRC
−−
ID
−−
DATA0LOW
DATA0HIGH
DATA1LOW
DATA1HIGH
REGISTER FUNCTION
Specifies register address
Control of basic functions
Integration time/gain control
Low byte of low interrupt threshold
High byte of low interrupt threshold
Low byte of high interrupt threshold
High byte of high interrupt threshold
Interrupt control
Reserved
Factory test — not a user register
Reserved
Part number/ Rev ID
Reserved
Low byte of ADC channel 0
High byte of ADC channel 0
Low byte of ADC channel 1
High byte of ADC channel 1
The mechanics of accessing a specific register depends on the specific SMB protocol used. Refer to the section
on SMBus protocols. In general, the COMMAND register is written first to specify the specific control/status
register for following read/write operations.
The LUMENOLOGY r Company
r
Copyright E 2008, TAOS Inc.
r
www.taosinc.com
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