TSC80251-SK Просмотр технического описания (PDF) - Temic Semiconductors
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TSC80251-SK Datasheet PDF : 52 Pages
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TSC87251G1A
Table 1. TSC87251G1A Pin Assignment
DIP PLCC
Name
1
VSS1
1
2
P1.0/T2
2
3
P1.1/T2EX
3
4
P1.2/ECI
4
5
P1.3/CEX0
5
6
P1.4/CEX1
6
7
P1.5/CEX2/MISO
7
8
P1.6/CEX3/SCL/SCK
8
9
P1.7/A17/CEX4/SDA/MOSI
9
10 RST
10
11 P3.0/RXD
12 NC
11
13 P3.1/TXD
12
14 P3.2/INT0#
13
15 P3.3/INT1#
14
16 P3.4/T0
15
17 P3.5/T1
16
18 P3.6/WR#
17
19 P3.7/A16/RD#
18
20 XTAL2
19
21 XTAL1
20
22 VSS
DIP PLCC
23 VSS2
21
24 P2.0/A8
22
25 P2.1/A9
23
26 P2.2/A10
24
27 P2.3/A11
25
28 P2.4/A12
26
29 P2.5/A13
27
30 P2.6/A14
28
31 P2.7/A15
29
32 PSEN#
30
33 ALE/PROG#
34 NC
31
35 EA#/VPP
32
36 P0.7/AD7
33
37 P0.6/AD6
34
38 P0.5/AD5
35
39 P0.4/AD4
36
40 P0.3/AD3
37
41 P0.2/AD2
38
42 P0.1/AD1
39
43 P0.0/AD0
40
44 VDD
Name
5.2. Signals
Table 2. TSC87251G1A Signal Descriptions
Signal
Name
A17
A16
A15:8(1)
AD7:0(1)
ALE
CEX4:0
EA#
Type
O
O
O
I/O
O
O
I
Description
Alternate
Function
18th Address Bit
P1.7
Output to memory as 18th external address bit (A17) in extended bus applications, depending
on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13).
17th Address Bit
P3.7
Output to memory as 17th external address bit (A16) in extended bus applications, depending
on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13).
Address Lines
Upper address lines for the external bus.
P2.7:0
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
P0.7:0
Address Latch Enable
ALE signals the start of an external bus cycle and indicates that valid address information are
available onlines A16/A17 and A7:0. An external latch can use ALE to demultiplex the address
from address/databus.
PCA Input/Output pins
P1.7:3
CEXx are input signals for the PCA capture mode and output signals for the PCA compare and
PWM modes.
External Access Enable
EA# directs program memory accesses to on–chip or off–chip code memory.
For EA#= 0, all program memory accesses are off-chip.
For EA#= 1, an access is on-chip EPROM/OTPROM if the address is within the range of the on–
chip EPROM/OTPROM; otherwise the access is off-chip. The value of EA# is latched at reset.
Rev. A – September 21, 1998
5
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