TRC104 Просмотр технического описания (PDF) - RF Monolithics, Inc

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TRC104

2.4 GHz RF Transceiver

RF Monolithics, Inc 

T R C 1 0 4 - M ic r o c o n tr o lle r S ig n a l C o n n e c tio n s

TR C 104

PM O DE

M ODE

CS

SC LK

SDAT

IN T

R S S ID

H ost

M ic r o c o n tr o lle r

Figure 18

The serial interface is enabled for read/write transactions with the configuration registers by holding the CS pin

high. The CS pin must remain high during the transmission of both the address and data bytes or the data will be

corrupted. Between each configuration register read/write transaction the serial interface must be reset by pulling

the CS pin low. Pulling CS high again re-enables the serial interface for a new configuration register read/write

transaction. Back-to-back configuration register read/writes are not possible as the configuration register address

is not automatically incremented. Refer to Sections 7.1 for additional configuration register access details.

The serial interface is enabled for read/write transactions with the FIFO by holding the CS pin low. Data and

clocking are handled through the SDAT and SCLK pins, respectively.

7.1 Configuration Registers Access

The most significant bit of each byte is sent first. The rising SCLK edge is used to sample the received bit, and the

falling SCLK edge shifts the data inside the shift register. The most significant bit of the first byte specifies a read

or write command followed by seven address bits. The following byte contains the read/write data.

Two bytes are required for each configuration register transaction. The first byte contains the R/W bit (0 = read,

1 = write) and the 7-bit configuration register address. The second byte contains the configuration value to be

written or read from the address specified in the first byte. Figure 19 and Table 14 show the timing for a

configuration read sequence from the TRC104.

C o n fig u r a tio n B y te R e a d T im in g

CS

SDAT

T1

R /W

A6

A5

A1

A0

D7

D6

D5

SC LK

T2

T3

T4

T5

Figure 19

D1

D0

T6

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Page 20 of 33

TRC104 - 08/13/09

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