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TRC104

2.4 GHz RF Transceiver

RF Monolithics, Inc 

0x09 - 0x0D, or by writing it directly before the payload data bytes. The source for the destination address is

chosen by the DesADD_ref bit in configuration register 0x05. When writing the destination address directly, the

most significant address byte is written first. Sender (local device) addressing is optional. If used, the sender

address is automatically loaded from configuration registers 0x0E - 0x12. The destination address can be from

one to five bytes in length. If used, the sender address must be the same length as the destination address.

S e r ia l P o r t B u r s t T r a n s m it M o d e T im in g

M ODE

IN T

SDAT

SC LK

T1

T3

T4

T2

T5

T6

Figure 13

Item Description

Min Typ Max Unit

T1 MODE to 1st Bit Time

20

µs

T2 SCLK Cycle Time

500

ns

T3 Setup Time

15

ns

T4 Hold Time

15

ns

T5 Address & Payload Data 8

296 bits

T6 Dummy Bit Writes

3 bits

Table 12

5.2.2 Burst Receive Mode

Burst Receive Mode is enabled when the C_Mode bit of register 0x00 is set to 0 and the D_Mode bit of register

0x02 is set to 1. In Burst Receive Mode, the FIFO is loaded with the payload data part of a received packet. The

automatic packet features listed in Section 5.2 are available for use in Burst Receive Mode. Using these features

frees up the host microcontroller to perform other tasks.

As a packet is received, the TRC104 uses the preamble to lock to the incoming data rate and then determines if

the packet is for it by testing the address following the preamble for a match to its own device address. If the

addresses match, the TRC104 receives the remainder of the packet, including the sender address if present, the

payload data and CRC. The TRC104 then performs a CRC calculation and compares the result with the received

CRC value. If the CRC’s match, the INT flag is asserted according to the interrupt polarity as configured by the

LVLINT bit of configuration register 0x17. Otherwise, the packet is discarded unless this default is overridden.

Upon assertion of the INT flag, the host microcontroller clocks out and discards two dummy bits, and then clocks

out received bits, checking the INT flag after each group of 8 bits. The INT flag will de-assert when the next-to-last

payload data byte in the FIFO is read. The host microcontroller then completes the read transaction by clocking

out the last FIFO byte followed by clocking out and discarding three more dummy bits. When the INT flag is

asserted the host microcontroller should read the data quickly so as not to delay listening for the next packet. If

the data has not been completely read when the next packet is transmitted, reception will not occur and the

transmitted data will be missed. Figure 14 and Table 13 show the serial port timing parameters for Burst Receive

Mode.

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Page 16 of 33

TRC104 - 08/13/09

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