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IDT723614L30PQF

CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2

Integrated Device Technology 

IDT723614 CMOS SyncBiFIFO™ WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION

Symbol

Name

A0-A35 Port A Data

AEA Port A Almost-Empty

Flag

AEB Port B Almost-Empty

Flag

AFA Port A Almost-Full

Flag

AFB Port B Almost-Full

Flag

B0-B35 Port B Data.

BE Big-endian select

CLKA Port A Clock

CLKB Port B Clock

CSA Port A Chip Select

CSB Port B Chip Select

EFA Port A Empty Flag

EFB Port B Empty Flag

ENA Port A Enable

ENB Port B Enable

FFA Port A Full Flag

FFB Port B Full Flag

I/O

Description

I/O 36-bit bidirectional data port for side A.

O Programmable almost-empty flag synchronized to CLKA. It is LOW when

(Port A) the number of 36-bit words in FIFO2 is less than or equal to the value in

the offset register, X.

O Programmable almost-empty flag synchronized to CLKB. It is LOW when the

(Port B) number of 36-bit words in FIFO1 is less than or equal to the value in the

offset register, X.

O Programmable almost-full flag synchronized to CLKA. It is LOW when the

(Port A) number of 36-bit empty locations in FIFO1 is less than or equal to the value

in the offset register, X.

O Programmable almost-full flag synchronized to CLKB. It is LOW when the

(Port B) number of 36-bit empty locations in FIFO2 is less than or equal to the value

in the offset register, X.

I/O 36-bit bidirectional data port for side B.

I Selects the bytes on port B used during byte or word data transfer. A LOW

on BE selects the most significant bytes on B0-B35 for use, and a HIGH

selects the least significant bytes

I CLKA is a continuous clock that synchronizes all data transfers through port A

and can be asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA

are synchronized to the LOW-to-HIGH transition of CLKA.

I CLKB is a continuous clock that synchronizes all data transfers through port B

and can be asynchronous or coincident to CLKA. Port B byte swapping and

data port sizing operations are also synchronous to the LOW-to-HIGH transi-

tion of CLKB. EFB, FFB, AFB, and AEB are synchronized to the LOW-to-HIGH

transition of CLKB.

I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or

write data on port A. The A0-A35 outputs are in the high-impedance state

when CSA is HIGH.

I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or

write data on port B. The B0-B35 outputs are in the high-impedance state

when CSB is HIGH.

O EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA is

(Port A) LOW, FIFO2 is empty, and reads from its memory are disabled. Data can

be read from FIFO2 to the output register when EFA is HIGH. EFA is forced

LOW when the device is reset and is set HIGH by the second LOW-to-HIGH

transition of CLKA after data is loaded into empty FIFO2 memory.

O EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is

(Port B) LOW, the FIFO1 is empty, and reads from its memory are disabled. Data can

be read from FIFO1 to the output register when EFB is HIGH. EFB is forced

LOW when the device is reset and is set HIGH by the second LOW-to-HIGH

transition of CLKB after data is loaded into empty FIFO1 memory.

I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or

write data on port A.

I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or

write data on port B.

O FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA is

(Port A) LOW, FIFO1 is full, and writes to its memory are disabled. FFA is forced LOW

when the device is reset and is set HIGH by the second LOW-to-HIGH transi-

tion of CLKA after reset.

O FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB is

(Port B) LOW, FIFO2 is full, and writes to its memory are disabled. FFB is forced LOW

when the device is reset and is set HIGH by the second LOW-to-HIGH transi-

tion of CLKB after reset.

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