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IDT723614L30

CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2

Integrated Device Technology 

IDT723614 CMOS SyncBiFIFO™ WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKB

FFB

CSB

W/RB

HIGH

ENB

SW1, SW0

tSZS

BE

tSZS

SIZ1, SIZ0

(0, 1)

tSZH

tSZH

Little

Endian

B0-B17

Big

Endian

B18-B35

ODD/EVEN

PEFB

tENS

tENS

tENS

tSWS

tSZS

tSZS

tDS

(0, 1)

tDS

tENH

tSWH

tSZH

tSZH

tDH

tDH

tENS

tENH

tENH

NOT (1,1) (1)

tPPE

VALID

tPDPE

VALID

NOTES:

3146 drw 07

1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register.

2. PEFB indicates parity error for the following bytes: B35-B27 and B26-B18 for big-endian bus, and B17-B9 and B-8-B0 for little-endian bus.

DATA SWAP TABLE FOR WORD WRITES TO FIFO2

SWAP

MODE

WRITE

NO.

DATA WRITTEN TO FIFO2

BIG ENDIAN

LITTLE ENDIAN

SW1 SW0

B35-27 B26-18

B17-B9

B8-B0

LL

1

A

B

C

D

2

C

D

A

B

LH

1

D

C

B

A

2

B

A

D

C

HL

1

C

D

A

B

2

A

B

C

D

HH

1

B

A

D

C

2

D

C

B

A

DATA READ FROM FIFO2

A35-27 A26-A18

A

B

A17-A9

C

A8-A0

D

A

B

C

D

A

B

C

D

A

B

C

D

Figure 7. Port-B Word Write Cycle Timing for FIFO2

20

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