IDT723614L30 Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723614L30

CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2

Integrated Device Technology 

IDT723614 CMOS SyncBiFIFO™ WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

CLKB

COMMERCIAL TEMPERATURE RANGE

FFB HIGH

tENS

CSB

W/RB

ENB

SW1,

SW0

tSZS

BE

tSZS

SIZ1,

SIZ0

Little B0-

Endian B8

Big B27-

Endian B35

(1,0)

tENS

tENS

tSWS

tSZH tSZS

tSZH tSZS

tDS

tDS

(1,0)

tENH

tENH

tSZH

tSZH

tDH

tDH

(1,0)

tENS

tENH

tENH

(1,0)

Not (1,1)(1)

ODD/EVEN

PEFB

tPPE

tPDPE

Valid

Valid

tPDPE

Valid

tPDPE

NOTES:

1. SIZ0 = HIGH amd SIZ1 = HIGH writes data to the mail2 register.

2. PEFB indicates parity error for the following bytes: B35—B27 for big-endian bus and B17—B9 for little-endian bus.

Valid

3146 drw 08

Figure 8. Port-B Byte Write Cycle Timing for FIFO2

21

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