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IDT723614

CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2

Integrated Device Technology 

IDT723614 CMOS SyncBiFIFO™ WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKB

FFB

CSB

W/RB

HIGH

ENB

SW1,

SW0

tSZS

BE

tSZH

tSZS

tSZH

SIZ1,

SIZ0

(0,0)

B0-B35

ODD/

EVEN

PEFB

t ENS

t ENS

t ENS

tSWS

tENH

tSWH

(0,0)

tDS

tDH

tPPE

VALID

NOTE:

1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register

NOT (1,1)(1)

tPDPE

VALID

tENS

tENH

3146 drw 06

DATA SWAP TABLE FOR LONG-WORD WRITES TO FIFO2

SWAP MODE

SW1 SW0

L

L

L

H

H

L

H

H

DATA WRITTEN TO FIFO2

B35-27 B26-18 B17-B9

B8-B0

A

B

C

D

D

C

B

A

C

D

A

B

B

A

D

C

DATA READ FROM FIFO2

A35-27

A26-A18 A17-A9

A

B

C

A

B

C

A

B

C

A

B

C

A8-A0

D

D

D

D

Figure 6. Port-B Long-Word Write Cycle Timing for FIFO2

19

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