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IDT723614

CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2

Integrated Device Technology 

IDT723614 CMOS SyncBiFIFO™ WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

BE SIZ1 SIZ0

HHL

B35—B27

B26—B18 B17—B9

B8—B0

D

B35—B27

B26—B18 B17—B9

B8—B0

C

B35—B27

B26—B18 B17—B9

B8—B0

B

B35—B27

B26—B18 B17—B9

B8—B0

A

(d) BYTE SIZE — LITTLE ENDIAN

1st: Read from FIFO1/

Write to FIFO2

2nd: Read from FIFO1/

Write to FIFO2

3rd: Read from FIFO1/

Write to FIFO2

4th: Read from FIFO1/

Write to FIFO2

3146 drw fig 01a

Figure 1. Dynamic Bus Sizing (continued)

DESCRIPTION (CONTINUED)

or both SIZ1 and SIZ0 are LOW and from the mail2 register

when both SIZ1 and SIZ0 are HIGH.The mail1 register flag

(MBF1) is set HIGH by a rising CLKB edge when a port B read

is selected by CSB, W/RB, and ENB with both SIZ1 and SIZ0

HIGH. The mail2 register flag (MBF2) is set HIGH by a LOW-

to-HIGH transition on CLKA when port A read is selected by

CSA, W/RA, and ENA and MBA is HIGH. The data in the mail

register remains intact after it is read and changes only when

new data is written to the register.

DYNAMIC BUS SIZING

The port B bus can be configured in a 36-bit long word,

18-bit word, or 9-bit byte format for data read from FIFO1 or

written to FIFO2. Word- and byte-size bus selections can

utilize the most significant bytes of the bus (big endian) or least

significant bytes of the bus (little endian). Port B bus size can

be changed dynamically and synchronous to CLKB to com-

municate with peripherals of various bus widths.

The levels applied to the port B bus size select (SIZ0,

SIZ1) inputs and the big-endian select (BE) input are stored on

each CLKB LOW-to-HIGH transition. The stored port B bus

size selection is implemented by the next rising edge on CLKB

according to Figure 1.

Only 36-bit long-word data is written to or read from the

two FIFO memories on the IDT723614. Bus-matching opera-

tions are done after data is read from the FIFO1 RAM and

before data is written to the FIFO2 RAM. Port B bus sizing

does not apply to mail register operations.

BUS-MATCHING FIFO1 READS

Data is read from the FIFO1 RAM in 36-bit long word

increments. If a long word bus size is implemented, the entire

long word immediately shifts to the FIFO1 output register. If

byte or word size is implemented on port B, only the first one

or two bytes appear on the selected portion of the FIFO1

output register, with the rest of the long word stored in auxiliary

registers. In this case, subsequent FIFO1 reads with the same

bus-size implementation output the rest of the long word to the

FIFO1 output register in the order shown by Figure1.

Each FIFO1 read with a new bus-size implementation

automatically unloads data from the FIFO1 RAM to its output

register and auxiliary registers. Therefore, implementing a

new port B bus size and performing a FIFO1 read before all

bytes or words stored in the auxiliary registers have been read

results in a loss of the unread long word data.

When reading data from FIFO1 in byte or word format, the

unused B0-B35 outputs remain inactive but static, with the

unused FIFO1 output register bits holding the last data value

to decrease power consumption.

BUS-MATCHING FIFO2 WRITES

Data is written to the FIFO2 RAM in 36-bit long word

increments. FIFO2 writes, with a long-word bus size, immedi-

ately store each long word in FIFO2 RAM. Data written to

FIFO2 with a byte or word bus size stores the initial bytes or

words in auxiliary registers. The CLKB rising edge that writes

the fourth byte or the second word of long word to FIFO2 also

stores the entire long word in FIFO2 RAM. The bytes are

arranged in the manner shown in Figure 1.

Each FIFO2 write with a new bus-size implementation

resets the state machine that controls the data flow from the

auxiliary registers to the FIFO2 RAM. Therefore, implement-

ing a new bus size and performing a FIFO2 write before bytes

or words stored in the auxiliary registers have been loaded to

FIFO2 RAM results in a loss of data.

13

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