IDT723614L20PFI(2002) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723614L20PFI
(Rev.:2002)

CMOS SyncBiFIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2

Integrated Device Technology 

IDT723614 CMOS SYNCBIFIFO™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

CLKB

FFB HIGH

CSB

W/RB

ENB

SW1,

SW0

tSZS

BE

tSZS

SIZ1,

SIZ0

Little- B0-

Endian B8

Big- B27-

Endian B35

(1,0)

tENS

tENS

tENH

tSWS

tSZH tSZS

tSZH tSZS

tDS

tDS

(1,0)

tENS

tENH

tSZH

tSZH

tDH

tDH

(1,0)

ODD/EVEN

PEFB

tPPE

tPDPE

Valid

Valid

tPDPE

(1,0)

Valid

tENS

tENH

tENH

Not (1,1) (1)

tPDPE

Valid

3146 drw09

NOTES:

1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register.

2. PEFB indicates parity error for the following bytes: B35—B27 for Big-Endian bus and B17—B9 for Little-Endian bus.

DATA SWAP TABLE FOR BYTE WRITES TO FIFO2

SWAP

MODE

WRITE

NO.

DATA WRITTEN TO FIFO2

BIG-ENDIAN

LITTLE-ENDIAN

DATA READ FROM FIFO2

SW1 SW0

B35-27

B8-B0

A35-27 A26-A18

A17-A9

A8-A0

1

A

L

L

2

B

3

C

4

D

1

D

L

H

2

3

C

B

4

A

1

C

H

L

2

3

D

A

4

B

1

B

H

H

2

3

A

D

4

C

D

C

B

A

B

C

D

A

A

B

C

A

B

C

D

D

B

A

D

A

B

C

D

C

C

D

A

A

B

C

D

B

Figure 9. Port-B Byte Write Cycle Timing for FIFO2

19

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