IDT723614L20PFI(2002) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723614L20PFI
(Rev.:2002)

CMOS SyncBiFIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2

Integrated Device Technology 

IDT723614 CMOS SYNCBIFIFO™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

tSKEW2 or greater after the write that fills the FIFO to (X+1) long words.

Otherwise, the subsequent synchronizing clock cycle can be the first

synchronization cycle (see Figure 18 and 19).

ALMOST FULL FLAGS (AFA, AFB)

The Almost-Full flag of a FIFO is synchronized to the port clock that writes

data to its array. The state machine that controls an Almost-Full flag

monitors a write-pointer and read-pointer comparator that indicates when

the FIFO SRAM status is almost full, almost full-1, or almost full-2. The

almost-full state is defined by the value of the Almost-Full and Almost-Empty

Offset register (X). This register is loaded with one of four preset values

during a device reset (see Reset above). An Almost-Full flag is LOW when

the FIFO contains (64-X) or more long words in memory and is HIGH when

the FIFO contains [64-(X+1)] or less long words.

Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock

are required after a FIFO read for the Almost-Full flag to reflect the new level

TABLE 1 — FLAG PROGRAMMING

FS1

FS0

RST

H

H

↑

H

L

↑

L

H

↑

L

L

↑

ALMOST-FULL AND

ALMOST-EMPTY FLAG

OFFSET REGISTER (X)

16

12

8

4

of fill. Therefore, the Almost-Full flag of a FIFO containing [64-(X+1)] or less

words remains LOW if two cycles of the synchronizing clock have not

elapsed since the read that reduced the number of long words in memory

to [64-(X+1)]. An Almost-Full flag is set HIGH by the second LOW-to-HIGH

transition of the synchronizing clock after the FIFO read that reduces the

number of long words in memory to [64-(X+1)]. A LOW-to-HIGH transition

of an Almost-Full flag synchronizing clock begins the first synchronization

cycle if it occurs at time tSKEW2 or greater after the read that reduces the number

of long words in memory to [64-(X+1)]. Otherwise, the subsequent synchro-

nizing clock cycle can be the first synchronization cycle (see Figure 20 and 21).

MAILBOX REGISTERS

Each FIFO has a 36-bit bypass register to pass command and control

information between port A and port B without putting it in queue. The

Mailbox-Select (MBA, MBB) inputs choose between a mail register and a

FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA

writes A0-A35 data to the mail1 register when a port A write is selected by

CSA, W/RA, and ENA with MBA HIGH. A LOW-to-HIGH transition on CLKB

writes B0-B35 data to the mail2 register when a port B write is selected by

CSB, W/RB, and ENB with both SIZ1 and SIZ0 HIGH. Writing data to a mail

register sets the corresponding flag (MBF1 or MBF2) LOW. Attempted

writes to a mail register are ignored while the mail flag is LOW.

When the port A data outputs (A0-A35) are active, the data on the bus

comes from the FIFO2 output register when MBA is LOW and from the mail2

register when MBA is HIGH. When the port B data outputs (B0-B35) are

active, the data on the bus comes from the FIFO1 output register when

either one or both SIZ1 and SIZ0 are LOW and from the mail2 register when

both SIZ1 and SIZ0 are HIGH. The Mail1 Register Flag (MBF1) is set HIGH

TABLE 2 — PORT-A ENABLE FUNCTION TABLE

CSA

W/RA

ENA

MBA

CLKA

H

X

X

X

X

L

H

L

X

X

L

H

H

L

↑

L

H

H

H

↑

L

L

L

L

X

L

L

H

L

↑

L

L

L

H

X

L

L

H

H

↑

A0-A35 Outputs

In High-Impedance State

In High-Impedance State

In High-Impedance State

In High-Impedance State

Active, FIFO2 Output Register

Active, FIFO2 Output Register

Active, Mail2 Register

Active, Mail2 Register

Port Functions

None

None

FIFO1 Write

Mail1 Write

None

FIFO2 Read

None

Mail2 Read (Set MBF2 HIGH)

TABLE 3 — PORT-B ENABLE FUNCTION TABLE

CSB W/RB ENB

H

X

X

L

H

L

L

H

H

L

H

H

L

L

L

L

L

H

L

L

L

L

L

H

SIZ1, SIZ0

X

X

One, both LOW

Both HIGH

One, both LOW

One, both LOW

Both HIGH

Both HIGH

CLKB

X

X

↑

↑

X

↑

X

↑

B0-B35 Outputs

In High-Impedance State

In High-Impedance State

In High-Impedance State

In High-Impedance State

Active, FIFO1 Output Register

Active, FIFO1 Output Register

Active, Mail1 Register

Active, Mail1 Register

Port Functions

None

None

FIFO2 Write

Mail2 Write

None

FIFO1 read

None

Mail1 Read (Set MBF1 HIGH)

11

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