IDT723632L Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723632L

CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2

Integrated Device Technology 

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2

CLKB

CSB

W/RB

MBB

ENB

tCLK

tCLKH

tCLKL

LOW

HIGH

LOW

tENS

tENH

COMMERCIAL TEMPERATURE RANGE

ORB

HIGH

tA

B0 -B35

Previous Word in FIFO1 Output Register

tSKEW1 (1)

Next Word From FIFO1

tCLK

tCLKH

tCLKL

CLKA

IRA

FIFO1 Full

1

2

tPIR

tPIR

CSA

LOW

WRA

MBA

HIGH

tENS

tENH

tENS

tENH

ENA

tDS

tDH

A0 - A35

To FIFO1

3022 drw 12

NOTE:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between

the rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.

Figure 9. IRA Flag Timing and First Available Write when FIFO1 is Full.

5.22

19

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