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723642L15

CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2

Integrated Device Technology 

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKA

CSA

LOW

tCLK

tCLKH tCLKL

WRA

MBA

ENA

HIGH tENS

tENS

tENH

tENH

IRA HIGH tDS

tDH

A0 - A35

CLKB

W1

(1)

tSKEW1

tCLK

tCLKH tCLKL

1

2

ORB

CSB

LOW

Old Data in FIFO1 Output Register

3

tPOR

tPOR

W/RB HIGH

MBB LOW

tENS

tENH

ENB

B0 -B35

tA

Old Data in FIFO1 Output Register

W1

3022 drw 10

NOTE:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output

register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and

load of the first word to the output register may occur one CLKB cycle later than shown.

Figure 7. ORB Flag Timing and First Data Word Fallthrough when FIFO1 is Empty.

5.22

17

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