723642L15 Просмотр технического описания (PDF) - Integrated Device Technology
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723642L15 Datasheet PDF : 26 Pages
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IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
OUTPUT-READY FLAGS (ORA, ORB)
The output-ready flag of a FIFO is synchronized to the port
clock that reads data from its array. When the output-ready
flag is HIGH, new data is present in the FIFO output register.
When the output-ready flag is LOW, the previous data word is
present in the FIFO output register and attempted FIFO reads
are ignored.
A FIFO read pointer is incremented each time a new word
is clocked to its output register. The state machine that
controls an output-ready flag monitors a write pointer and read
pointer comparator that indicates when the FIFO SRAM
status is empty, empty+1, or empty+2. From the time a word
is written to a FIFO, it can be shifted to the FIFO output register
in a minimum of three cycles of the output-ready flag synchro-
nizing clock. Therefore, an output-ready flag is LOW if a word
in memory is the next data to be sent to the FlFO output
register and three cycles of the port Clock that reads data from
the FIFO have not elapsed since the time the word was
written. The output-ready flag of the FIFO remains LOW until
the third LOW-to-HIGH transition of the synchronizing clock
occurs, simultaneously forcing the output-ready flag HIGH
and shifting the word to the FIFO output register.
A LOW-to-HIGH transition on an output-ready flag syn-
chronizing clock begins the first synchronization cycle of a
write if the clock transition occurs at time tSKEW1 or greater
after the write. Otherwise, the subsequent clock cycle can be
the first synchronization cycle (see Figures 7 and 8).
INPUT-READY FLAGS (IRA, IRB)
The input-ready flag of a FlFO is synchronized to the port
clock that writes data to its array. When the input-ready flag
is HIGH, a memory location is free in the SRAM to receive new
data. No memory locations are free when the input-ready flag
is LOW and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pointer is
incremented. The state machine that controls an input-ready
flag monitors a write pointer and read pointer comparator that
indicates when the FlFO SRAM status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory
location is ready to be written in a minimum of two cycles of the
IDT723622(1,2)
0
Number of Words in FIFO
IDT723632(1,2)
0
IDT723642(1,2)
0
1 to X1
1 to X1
1 to X1
(X1+1) to [256-(Y1+1)] (X1+1) to [512-(Y1+1)] (X1+1) to [1024-(Y1+1)]
(256-Y1) to 255
(512-Y1) to 511
(1024-Y1) to 1023
256
512
1024
S ynchronized
to CLKB
ORB
AEB
L
L
H
L
H
H
H
H
H
H
Synchronized
to CLKA
AFA
IRA
H
H
H
H
H
H
L
H
L
L
Table 4. FIF01 Flag Operatlon
Notes:
1. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1
and Y1 are selected during a reset of FIFO1 or programmed from port A.
2. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
IDT723622(1,2)
0
Number of Words in FIFO
IDT723632(1,2)
0
IDT723642(1,2)
0
1 to X2
1 to X2
1 to X2
(X2+1) to [256-(Y2+1)] (X2+1) to [512-(Y2+1)] (X2+1) to [1024-(Y2+1)]
(256-Y2) to 255
(512-Y2) to 511
(1024-Y2) to 1023
256
512
1024
S ynchronized
to CLKA
ORA
AEA
L
L
H
L
H
H
H
H
H
H
Synchronized
to CLKB
AFB
IRB
H
H
H
H
H
H
L
H
L
L
Table 5. FIF02 Flag Operatlon
Notes:
1. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFB. Both X2 and
Y2 are selected during a reset of FIFO2 or programmed from port A.
2. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
5.22
12
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