IDT723642L(2015) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723642L
(Rev.:2015)

CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Integrated Device Technology 

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS (CONTINUED)

Symbol

Name

I/O

Description

ORA

Output Ready

O

ORA is synchronized to the LOW-to-HIGH transition of CLKA. When ORA is LOW, FIFO2 is

Flag

(Port A) empty and reads from its memory are disabled. Ready data is present on the output register

of FIFO2 when ORA is HIGH. ORA is forced LOW when FlFO2 is reset and goes HIGH on the

third LOW-to-HIGH transition of CLKA after a word is loaded to empty memory.

ORB

Output Ready

O

ORB is synchronized to the LOW-to-HIGH transition of CLKB. When ORB is LOW, FlFO1 is

Flag

(Port B) empty and reads from its memory are disabled. Ready data is present on the output register of FIFO1

when ORB is HIGH. ORB is forced LOW when FIFO1 is reset and goes HIGH on the third LOW-to-

HIGH transition of CLKB after a word is loaded to empty memory.

RST1

FIFO1 Reset

I

To reset FIFO1, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB

must occur while RST1 is LOW. The LOW-to-HIGH transition of RST1 latches the status of FS0

and FS1 for AFA and AEB offset selection. FIFO1 must be reset upon power up before data is

written to its RAM.

RST2

FIFO2 Reset

I

To reset FIFO2, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB

must occur while RST2 is LOW. The LOW-to-HIGH transition of RST2 latches the status of FS0

and FS1 for AFB and AEA offset selection. FIFO2 must be reset upon power up before data is

written to its RAM.

W/RA

Port A Write/

Read Select

I

A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH

transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.

W/RB

Port B Write/

Read Select

I

A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH

transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is LOW.

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