IDT723622L15PFG8(2015) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723622L15PFG8
(Rev.:2015)

CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Integrated Device Technology 

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

CLKA

CSA

tCLK

tCLKH

tCLKL

LOW

W/RA LOW

MBA LOW

ENA

tENS2

tENH

COMMERCIAL TEMPERATURE RANGE

ORA HIGH

tA

A0 -A35

Previous Word in FIFO2 Output Register

Next Word From FIFO2

tSKEW1(1)

tCLK

tCLKH

tCLKL

CLKB

1

2

tPIR

tPIR

IRB FIFO2 FULL

CSB LOW

W/RB LOW

MBB

tENS2

tENS2

tENH

tENH

ENB

tDS

tDH

B0 - B35

Wriite

To FIFO2

3022 drw 13

NOTE:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising

CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.

Figure 11. IRB Flag Timing and First Available Write when FIFO2 is Full

CLKA

tENS2

tENH

ENA

CLKB

AEB X1 Words in FIFO1

(1)

tSKEW2

1

2

tPAE

tPAE

(X1+1) Words in FIFO1

tENS2

tENH

ENB

3022 drw 14

NOTES:

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge

and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.

2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.

Figure 12. Timing for AEB when FIFO1 is Almost-Empty

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