IDT723622L15PFG8(2015) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723622L15PFG8
(Rev.:2015)

CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Integrated Device Technology 

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

Otherwise, the subsequent synchronizing clock cycle may be the first

synchronization cycle. (See Figures 12 and 13).

ALMOST-FULL FLAGS (AFA, AFB)

The Almost-Full flag of a FIFO is synchronized to the port clock that

writes data to its array. The state machine that controls an Almost-Full flag

monitors a write pointer and read pointer comparator that indicates when

the FIFO memory status is almost-full, almost-full-1, or almost-full-2. The

almost-full state is defined by the contents of register Y1 for AFA and

register Y2 for AFB. These registers are loaded with preset values during

a FlFO reset or programmed from port A (see Almost-Empty flag and

Almost-Full flag offset programming section). An Almost-Full flag is

LOW when the number of words in its FIFO is greater than or equal to

(256-Y), (512-Y), or (1,024-Y) for the IDT723622, IDT723632, or

IDT723642 respectively. An Almost-Full flag is HIGH when the number

of words in its FIFO is less than or equal to [256-(Y+1)], [512-(Y+1)], or

[1,024-(Y+1)] for the IDT723622, IDT723632, or IDT723642 respec-

tively. Note that a data word present in the FIFO output register has been

read from memory.

Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock

are required after a FIFO read for its Almost-Full flag to reflect the new level of

fill. Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-(Y+1)]

or less words remains LOW if two cycles of its synchronizing clock have not

elapsed since the read that reduced the number of words in memory to [256/

512/1,024-(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-

to-HIGH transition of its synchronizing clock after the FIFO read that

reduces the number of words in memory to [256/512/1,024-(Y+1)]. A

LOW-to-HIGH transition of an Almost-Full flag synchronizing clock begins

the first synchronization cycle if it occurs at time tSKEW2 or greater after the

read that reduces the number of words in memory to [256/512/1,024-

(Y+1)]. Otherwise, the subsequent synchronizing clock cycle may be the

first synchronization cycle (see Figures 14 and 15).

MAILBOX REGISTERS

Each FIFO has a 36-bit bypass register to pass command and control

information between port A and port B without putting it in queue. The

Mailbox select (MBA, MBB) inputs choose between a mail register and a

FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA

writes A0-A35 data to the mail1 register when a port A Write is selected by CSA,

W/RA, and ENA and with MBA HIGH. A LOW-to-HIGH transition on CLKB writes

B0-B35 data to the mail2 register when a port B Write is selected by CSB, W/

RB, and ENB and with MBB HIGH. Writing data to a mail register sets its

corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register

are ignored while the mail flag is LOW.

When data outputs of a port are active, the data on the bus comes from

the FIFO output register when the port Mailbox select input is LOW and from

the mail register when the port-mailbox select input is HIGH. The Mail1

Register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when

a port B Read is selected by CSB, W/RB, and ENB and with MBB HIGH. The

Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA

when a port A read is selected by CSA, W/RA, and ENA and with MBA HIGH.

The data in a mail register remains intact after it is read and changes only when

new data is written to the register. For mail register and Mail Register flag timing

diagrams, see Figure 16 and 17.

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