IDT72261L20PF Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72261L20PF

CMOS SUPERSYNC FIFO™ 16,384 x 9, 32,768 x 9

Integrated Device Technology 

IDT72261/72271 SyncFIFO™

16,384 x 9, 32,768 x 9

RCLK

tENS

REN

EF

Q0 - Q8

tOLZ

OE

WCLK

WEN

D0 - D8

MILITARY AND COMMERCIAL TEMPERATURE RANGES

tCLKH

tCLK

tCLKL

tENH

tREF

NO OPERATION

tREF

tA

tOE

LAST WORD

tOHZ

(1)

tFWL1

tENS

tENH

tDS

FIRST WORD

tDHS

3036 drw 10

NOTES:

1. tFWL1 contributes a variable delay to the overall first word latency (this parameter includes delays due to skew):

tFWL1 max. (in ns) = 10*Tf + 2* TRCLK

where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period

2. LD = HIGH

Figure 7. Read Cycle Timing (IDT Standard Mode)

17

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