IDT71028S17Y Просмотр технического описания (PDF) - Integrated Device Technology
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IDT71028S17Y Datasheet PDF : 7 Pages
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IDT71028
CMOS STATIC RAM 1 MEG (256K x 4-BIT)
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
ADDRESS
tRC
tAA
OE
CS
DATAOUT
tOE
tOLZ (5)
tCLZ (5)
tACS (3)
HIGH IMPEDANCE
tPU
VCC SUPPLY ICC
CURRENT ISB
COMMERCIAL TEMPERATURE RANGE
tOHZ (5)
tCHZ (5)
DATAOUT VALID
tPD
2966 drw 05
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
ADDRESS
DATAOUT
tRC
tAA
tOH
PREVIOUS DATAOUT VALID
tOH
DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
2966 drw 6
9.4
5
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