IDT72141L35P Просмотр технического описания (PDF) - Integrated Device Technology
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IDT72141L35P Datasheet PDF : 13 Pages
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IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
Single Device Configuration
In the standalone case, the SOX line is tied HIGH and not
used. On the first LOW-to-HIGH of the SOCP clock, all of the
Data Set lines (Q4, Q6, Q7, Q8) go LOW and a new serial word
is started. The Data Set lines then go HIGH on the equivalent
SOCP clock pulse. This continues until the Q line connected
to NR goes HIGH completing the serial word. The cycle is then
repeated with the next LOW-to-HIGH transition of SOCP.
SERIAL OUTPUT CLOCK
V CC
PARALLEL DATA IN
SOCP
SOX
NR
D 0-7
SO
XI
Q4 Q6 Q7 Q8
SERIAL DATA OUTPUT
GND
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
SOCP
Q4
Q6
Q7
NR
2751 drw 15
Figure 12. Eight-Bit Word Single Device Configuration
TRUTH TABLES
TABLE 1: RESET AND RETRANSMIT —
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Mode
Inputs
RS
FL/RT
XI
Internal Status
Read Pointer
Write Pointer
Reset
0
X
0
Location Zero
Location Zero
Retransmit
1
0
0
Location Zero
Unchanged
Read/Write
1
1
0
Increment(1)
Increment(1)
NOTE:
1. Pointer will increment if appropriate flag is HIGH.
AEF, EF
0
X
X
Outputs
FF
1
X
X
HF
1
X
X
2751 tbl 09
5.34
10
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