RF5C62 Просмотр технического описания (PDF) - RICOH Co.,Ltd.
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RF5C62 Datasheet PDF : 48 Pages
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RP/RF/RS5C62
2.5 Interrupt Cycle Selection Register (BANK1 at “0h”)
D3
D2
D1
D0
CT3
CT2
CT1
CT0 (For write operation)
0
0
0
0
(For read operation) *1
Interrupt cycle/output mode selection bits *2
*1) These bits are intended for only write operation and always read as “0”.
*2) The CT3 to CT0 bits are used to set interrupt cycles and output modes as shown in the table below:
CT3
CT2
CT1
CT0
INTR
Remarks
*
0
*
0
*
0
*
0
*
1
*
1
*
1
*
1
0
*
1
*
0
0
“OFF”
Disable a cyclic interrupt.
0
1
2048Hz
Specify a cycle (T) of 0.488ms (1/2048Hz).
1
0
1024Hz
Specify a cycle (T) of 0.977ms (1/1024Hz).
1
1
128Hz
Specify a cycle (T) of 7.813ms (1/128Hz).
0
0
16Hz
Specify a cycle (T) of 62.5ms (1/16Hz).
0
1
1Hz
Specify a cycle (T) of 1s (1/1Hz).
1
0
1/60Hz
Specify a cycle (T) of 60s (1/1/60Hz).
1
1
“ON”
Specify the fixed low level of the INTR pin output.
*
*
Pulse mode Specify a duty cycle of 50%. See below.
*
*
Level mode See below.
* * ) The bits marked with “ ” are set to “0” or “1”.
• Pulse mode
(The CT3 bit is set to “0”.)
(The CTFG bit is not intended for write operation.)
CTFG
INTR
Preset interrupt cycle
• Level mode
(The CT3 bit is set to “1”.)
(The CTFG bit is intended for setting to “0” only.)
• Relationship between INTR pin output and
upward second count
CTFG
INTR
Interrupt
(Interrupt) Setting the CTFG bit to “0”
(1) Pulse mode (when 1Hz or 1/60Hz is selected)
INTR
30.5µs
Upward second count
(2) Level mode (when 1Hz or 1/60Hz is selected)
INTR
30.5µs
Upward second count
Upward second count
Upward second count
11
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