RF5C62 Просмотр технического описания (PDF) - RICOH Co.,Ltd.

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RF5C62

REAL-TIME CLOCK

RICOH Co.,Ltd. 

RP/RF/RS5C62

2.2 Control Register 2 (BANK0/1 at “Eh”)

D3

**1

BSY

D2

CTFG

CTFG

D1

ALFG

ALFG

D0

XSTP

XSTP

(For write operation)

(For read operation)

Oscillation stop detection bit *2

XSTP

Function

0

Indicates the progress of oscillation. Intended for setting to “0”.

1

Indicates the stop of oscillation. Not intended for setting to “1”.

Alarm time match indication bit *3

ALFG

Function

0

Indicates an alarm interrupt is disabled or indicates mismatching between clock

time and alarm time (upon turning off the INTR pin). Intended for setting to “0”.

1

Indicates matching between clock time and alarm time (upon driving low the

INTR pin). Not intended for setting to “0”.

Cyclic interrupt indication bit *4

CTFG

Function

0

Indicates that the INTR pin is turned off. Intended for setting to “0” in the level

mode.

1

Indicates that the INTR pin is driven low. Not intended for setting to “0”.

Time/calendar counter state indication bit *5

BSY

Function

0

Indicates the normal state of the time and calendar counters (no carry or no

reset pulse).

1

Indicates the busy state of the time and calendar counters (a carry or a reset

pulse generated).

*1) The BSY bit is intended for only read operation and is not intended for write operation.

*2) The XSTP bit is used to detect the stop of the crystal oscillator. The XSTP bit is set to “1” upon the stop of oscillation and held at “1” after the restart

of oscillation. Upon detection of the stop of oscillation, the built-in timer counter is reset (because the TM3 bit in the timer clock selection register is

reset).

*3) When the ALEN bit is set to “1”, the ALFG bit is also set to “1” upon output of an alarm interrupt from the INTR pin (while it is held low).

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