IDT723613L30PQF Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

IDT723613L30PQF

CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36

Integrated Device Technology 

IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36

COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION (CONTINUED)

Symbol

ODD/

EVEN

PEFA

PEFB

PGA

PGB

RST

SIZ0,

SIZ1

Name

Odd/Even Parity

Select

Port A Parity Error

Flag

Port B Parity Error

Flag

Port A Parity

Generation

Port B Parity

Reset

Port B Bus Size

Selects

I/O

I

O

(Port A)

O

(Port B)

I

I

I

I

(Port B)

Description

Odd parity is checked on each port when ODD/EVEN is HIGH, and even

parity is checked when ODD/EVEN is LOW. ODD/EVEN also selects the

type of parity generated for each port if parity generation is enabled for a read

operation.

When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes

are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the most

significant bit of each byte serving as the parity bit. The type of parity

checked is determined by the state of the ODD/EVEN input.

The parity trees used to check the A0-A35 inputs are shared by the mail2

register to generate parity if parity generation is selected by PGA. Therefore, if

a mail2 read with parity generation is set up by having CSA LOW, ENA HIGH,

W/RA LOW, MBA HIGH and PGA HIGH, the PEFA flag is forced HIGH

regardless of the state of the A0-A35 inputs.

When any valid byte applied to terminals B0-B35 fails parity, PEFB is LOW.

Bytes are organized as B0-B8, B9-B17, B-18-B26, and B27-B35, with the

most significant bit of each byte serving as the parity bit. A byte is valid when

it is used by the bus size selected for port B. The type of parity checked is

determined by the state of the ODD/EVEN input.

The parity trees used to check the B0-B35 inputs are shared by the mail1

register to generate parity if parity generation is selected by PGB. Therefore, if

a mail1 read with parity generation is set up by having CSB LOW, ENB HIGH,

W/RB LOW, SIZ1 and SIZ0 HIGH and PGB HIGH, the PEFB flag is forced

HIGH regardless of the state of the B0-B35 inputs.

Parity is generated for data reads from the mail2 register when PGA is HIGH.

The type of parity generated is selected by the state of the ODD/EVEN input.

Bytes are organized at A0-A8, A9-A17, A18-A26, and A27-A35. The gener-

ated parity bits are output in the most significant bit of each byte.

Parity is generated for data reads from port B when PGB is HIGH. The type of

parity generated is selected by the state of the ODD/EVEN input. Bytes are

organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity

bits are output in the most significant bit of each byte.

To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-

HIGH transitions of CLKB must occur while RST is LOW. This sets the AF,

MBF1, and MBF2 flags HIGH and the EF, AE, and FF flags LOW. The LOW-

to-HIGH transition of RST latches the status of the FS1 and FS0 inputs to

select almost-full flag and almost-empty flag offset.

A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and BE,

and the following LOW-to-HIGH transition of CLKB implements the latched

states as a port B bus size. Port B bus sizes can be long word, word, or byte.

A HIGH on both SIZ0 and SIZ1 accesses the mailbox registers for a port B 36-bit

write or read.

SW0,

SW1

W/RA

W/RB

Port B Byte Swap

Selects

Port A Write/Read

Select

Port B Write/Read

Select

I

(Port B)

I

I

At the beginning of each long word FIFO read, one of four modes of byte-

order swapping is selected by SW0 and SW1. The four modes are no swap,

byte swap, word swap, and byte-word swap. Byte-order swapping is possible

with any bus-size selection.

A HIGH selects a write operation and a LOW selects a read operation on

port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the

high-impedance state when W/RA is HIGH.

A HIGH selects a write operation and a LOW selects a read operation on

port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the

high-impedance state when W/RB is HIGH.

5

Share Link: