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IDT723613L30PF

CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36

Integrated Device Technology 

IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36

COMMERCIAL TEMPERATURE RANGES

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

vs

CLOCK FREQUENCY

400

350

f data = 1/2 f s

T A = 25 ° C

300

C L = 0 pF

VCC = 5.5 V

250

200

150

VCC = 5 V

VCC = 4.5 V

100

50

0

0

10

20

30

40

50

60

70

80

f s – Clock Frequency – MHz

3145 drw 19

FIGURE 19

CALCULATING POWER DISSIPATION

The ICCf current for the graph in Figure 19 was taken while simultaneously reading and writing the FIFO on the

IDT723613 with CLKA and CLKB set to fs. All date inputs and data outputs change state during each clock cycle to

consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-copacitance load.

Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with the equation

below.

With ICC(f) taken from Figure 19, the maximum power dissipation (PT) of the IDT723613 may be calculated by:

PT = VCC x ICC(f) + ∑[CL x (VOH - VOL)2 x fO)

where:

CL

=

fo

=

output capacitive load

switching frequency of an output

VOH =

output high-level voltage

VOL =

output high-level voltage

When no reads or writes are occurring on the IDT723613, the power dissipated by a single clock (CLKA or CLKB)

input running at frequency fs is calculated by:

PT = VCC x fs x 0.29ma/MHz

27

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