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XRD66092AID

CMOS 750 KSPS, 12-Bit Analog-to-Digital Converter with Serial Logic Interface Port

Exar Corporation 

CLK

Analog

Input

VIN

DATA

1/FS

tPWH tPWL

N+1

N+2

Pipeline Delay

tAP

N

N+1

N+2

Sampling

Points

N–3

N–2

tDL

N–1

XRD66092

N+3

N

N+1

Figure 1. XRD66092 Timing Diagram

DNL LSB

Analog

Input

V(N+1)

V(N)

Output

Codes

Code Width (N) = V(N+1) – V(N)

LSB = [ VRT – VRB ] / 4096

DNL(N) = [ V(N+1) – V(N) ] – LSB

N+1

N

N–1

Figure 2. DNL Measurement

Output

Codes

7

Real Transfer Line

6

5

INL

4

3

2

1

LSB

Best Fit Line

EFS

Ideal Transfer Line

EZS

Analog Input (Volt)

Figure 3. INL Error Calculation

UFW: Underflow (Output)

This signal indicates when the Analog Input (VIN) goes below

the VRB range, and is normally at a low logic level. When VIN <

VRB, UFW will go high and the data bits will show negative full

scale (i.e. all 0’s if MINV & LINV are low).

OFW: Underflow (Output)

This signal indicates when the Analog Input (VIN) goes above

the VRB range, and is normally at a low logic level. When VIN >

VRB, OFW will go high and the data bits will show positive full

scale (i.e. all 0’s if MINV & LINV are low).

SDO: Serial Data output

After the internal shift register is updated using the PLOAD

signal, the SDO pin outputs the A/D result starting with the MSB

Rev. 1.00

(which appears just after the PLOAD strobe). Each bit is output

on the rising edge of SCLK.

SCLK: Serial Data Port Clock

The SCLK controls the output of the serial port through SDO.

SDO is updated on every rising edge of SCLK. The PLOAD sig-

nal will override the SCLK signal.

PLOAD:

Serial data port shift register load: When PLOAD is low (i.e.

level triggered not edge triggered) the current parallel data will

be loaded into the shift register. PLOAD overrides SCLK. When

PLOAD is high, the data can be shifted out through the SDO pin

with SCLK.

5

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