CDP1883 Просмотр технического описания (PDF) - Intersil
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CDP1883 Datasheet PDF : 6 Pages
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WAIT
CLR
TPA
CDP1800
SERIES
CPU
MRD
MWR
CDP1883, CDP1883C
ADDRESS BUS
A0 - A7
TPA
CDP1837C
4K x 8
ROM
CEO
MRD
A0 - A6
CLK
CDP1883
LATCH/
DECODER
CS0
CE
CS1
CS2
CS3
A8 - A12
A0 - A7
CDM6264
8K x 8
RAM
CE
OE
WE
DATA BUS
FIGURE 2. MINIMUM CDP1800-SYSTEM USING THE CDP1883 INTERFACE WITH AN 8K X 8-BIT MEMORY
WAIT
CLR
CDP1883
LATCH/
DECODER
CS3
CLK
CS2
CE
CS1
CS0
MA0 - MA6
A8 - A12
ADDRESS BUS
TPA
CDP1800
SERIES
CPU
ADDRESS BUS
MRD
A8 - A12
CE
A0 - A7
CDM5364
8K x 8
ROM
A8 - A12
CE
A0 - A7
CDM5364
8K x 8
ROM
A8 - A12
CE
A0 - A7
CDM5364
8K x 8
ROM
DATA BUS
FIGURE 3. 32K-BYTE ROM SYSTEM USING THE CDP1883
4-134
A8 - A12
CE
A0 - A7
CDM5364
8K x 8
ROM
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