LH5PV16256 Просмотр технического описания (PDF) - Sharp Electronics
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LH5PV16256 Datasheet PDF : 14 Pages
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CMOS 4M (256 × 16) Pseudo-Static RAM
LH5PV16256
AC ELECTRICAL CHARACTERISTICS 1,2,7 (TA = 0 to +70°C, VCC = 3.0 V ± 0.15 V)
PARAMETER
SYMBOL MIN. MAX. UNIT NOTES
Random read, write cycle time
Random modify write cycle time
CE pulse width
CE precharge time
Address setup time
Row address hold time from CE
Column address hold time from CE
CS setup time from CE
CS hold time from CE
Read command setup time
Read command hold time
CE access time
OE access time
CE to output in Low-Z
OE to output in Low-Z
Write disable to output in Low-Z
Chip disable to output in High-Z
Output disable to output in High-Z
WE to output in High-Z
Write command pulse width
Write command setup time
Write command hold time
Data setup time from write disable
Data setup time from chip disable
Data hold time from write disable
Data hold time from chip disable
Data hold time from column address
Column address hold time from chip disable
Column address hold time from write disable
Transition time (rise and fall)
Output disable setup time
Output disable hold time
Refresh time interval (2048 cycle)
Auto refresh cycle time
Refresh delay time from CE
Refresh pulse width (Auto refresh)
Refresh precharge time (Auto refresh)
CE delay time from refresh enable
(Auto refresh)
Refresh pulse width (Self refresh)
CE delay time from refresh precharge
(Self refresh)
VCC recovery time from data retention
Refresh setup hold time
Refresh disable hold time
Chip disable delay time from RFSH
tRC
tRMW
tCE
tP
tAS
tRAH
tCAH
tCSS
tCSH
tRCS
tRCH
tCEA
tOEA
tCLZ
tOLZ
tWLZ
tCHZ
tOHZ
tWHZ
tWCP
tWCS
tWCH
tDSW
tDSC
tDHW
tDHC
tOH
tAHC
tAHW
tT
tODS
tODH
tREF
tFC
tRFD
tFAP
tFP
tFCE
tFAS
tFRS
tR
tFS
tRDH
tRDD
190
ns
250
ns
120 10,000 ns
60
ns
0
ns
30
ns
120
ns
0
ns
30
ns
0
ns
0
ns
120
ns
60
ns
20
ns
0
ns
0
ns
0
30
ns
0
30
ns
0
30
ns
35
ns
35 10,000 ns
120 10,000 ns
30
ns
30
ns
0
ns
30
ns
0
ns
20
ns
0
ns
3
50
ns
0
ns
15
ns
32
ms
190
ns
90
ns
80 1,000 ns
40
ns
190
ns
8,000
ns
600
ns
5
ms
0
ns
15
ns
15
ns
3
3
11
9
4
4
11
9, 13
13
10, 13
12, 13
5, 12, 13
5
5, 11, 13
5
5
5, 13
6
6
8
8
5
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