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TEA1206

High efficiency DC/DC converter

Philips Electronics 

Philips Semiconductors

High efficiency DC/DC converter

Preliminary specification

TEA1206T

PINNING

SYMBOL

U/D

ILIM

UPOUT/DNIN

LX

SYNC

GND

FB

SHDWN

PIN

DESCRIPTION

1 conversion mode selection input

2 current limit resistor connection

3 up mode; output voltage/

down mode; input voltage

4 inductor connection

5 synchronization clock input

6 ground

7 feedback input

8 shut-down input

handbook, halfpage

U/D 1

8 SHDWN

ILIM 2

7 FB

TEA1206T

UPOUT/DNIN 3

6 GND

LX 4

5 SYNC

MGM667

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION

Control mechanism

The TEA1206T DC/DC converter is able to operate in PFM

(discontinuous conduction) or PWM (continuous

conduction) operation. All switching actions are completely

determined by a digital control circuit which uses the

output voltage level as its control input. This novel digital

approach enables the use of a new pulse width and

frequency modulation scheme, which ensures optimum

power efficiency over the complete range of operation of

the converter. The scheme works as follows.

When high output power is requested, the device will

operate in PWM (continuous conduction) mode.

This results in minimum AC currents in the circuit

components and hence optimum efficiency, cost and

EMC. In this mode, the output voltage is allowed to vary

between two predefined voltage levels. As long as the

output voltage stays within this so-called window,

switching continues in a fixed pattern. When the output

voltage reaches one of the window borders, the digital

controller immediately reacts by adjusting the pulse width

and inserting a current step in such a way that the output

voltage stays within the window with higher or lower

current capability. This approach enables very fast

reaction to load variations.

Figure 3 shows the converter’s response to a sudden load

increase. The upper trace shows the output voltage.

The ripple on top of the DC level is a result of the current

in the output capacitor, which changes in sign twice per

cycle, times the capacitor’s internal Equivalent Series

Resistance (ESR). After each ramp-down of the inductor

current, i.e. when the ESR effect increases the output

voltage, the converter determines what to do in the next

cycle. As soon as more load current is taken from the

output the output voltage starts to decay. When the output

voltage becomes lower than the low limit of the window,

a corrective action is taken by a ramp-up of the inductor

current during a much longer time. As a result, the DC

current level is increased and normal PWM control can

continue. The output voltage (including ESR effect) is

again within the predefined window.

Figure 4 depicts the spread of the output voltage window.

The absolute value is most dependent on spread, while the

actual window size is not affected. For one specific device,

the output voltage will not vary more than 2% typically.

In low output power situations, TEA1206T will switch over

to PFM (discontinuous conduction) mode operation. In this

mode, regulation information from earlier PWM mode

operation is used. This results in optimum inductor peak

current levels in PFM mode, which are slightly larger than

the inductor ripple current in PWM mode. As a result, the

transition between PFM and PWM mode is optimal under

all circumstances. In PFM mode, TEA1206T regulates the

output voltage to the high window limit shown in Fig.3.

Synchronous rectification

For optimal efficiency over the whole load range,

synchronous rectifiers inside TEA1206T ensure that

during the whole second switching phase, all inductor

current will flow through the low-ohmic power MOSFETS.

Special circuitry is included which detects that the inductor

current reaches zero. Following this detection, the digital

controller switches off the power MOSFET and proceeds

regulation.

1999 Sep 16

5

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