TB2104F Просмотр технического описания (PDF) - Toshiba

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TB2104F

TOSHIBA Bi−CMOS Integrated Circuit Silicon Monolithic

Toshiba 

5. T-BUS mode timing chart

TB2104F

· fCLK ≤ 500kHz

· t1 ≥ 0.2µs, t2 ≥ 0.2µs

· t3 ≥ 1.0µs, t4 ≥ 1.0µs

Cautions for use

· Therefore, multiple driver outputs may possibly become “H” level simultaneously after the power is turned

on.

(In this case, the allowable power dissipation of a device using this IC may possible be exceeded, destroying

the device.)

· In order to avoid this, while keeping the clear terminal (CL) at “L” level, rise the power supply for the logic

unit (VDD) and then, that for the drivers (VDR), reset all the contents of the data latch (“L” level) by serial

data, and initialize the driver outputs.

5

2002-10-30

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