SMD5962-92324 Просмотр технического описания (PDF) - Cypress Semiconductor
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SMD5962-92324 Datasheet PDF : 15 Pages
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STK11C68-5 (SMD5962-92324)
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [10, 11]
Parameter
Alt
tRC
tSA[10]
tCW[10]
tHACE[10]
tRECALL[10]
tAVAV
tAVEL
tELEH
tELAX
Description
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
35 ns
Min Max
35
0
25
20
20
45 ns
Min Max
45
0
30
20
20
Switching Waveform
Figure 11. CE Controlled Software STORE/RECALL Cycle [10]
55 ns
Unit
Min Max
55
ns
0
ns
35
ns
20
ns
20 μs
ADDRESS
CE
OE
tRC
ADDRESS # 1
tSA
tSCE
tHACE
DQ (DATA)
DATA VALID
tRC
ADDRESS # 6
t / t STORE RECALL
HIGH IMPEDANCE
DATA VALID
Notes
10. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).
11. The six consecutive addresses must be read in the order listed in Table 1 on page 4. WE must be HIGH during all six consecutive cycles.
Document Number: 001-51001 Rev. *A
Page 10 of 15
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