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ST5080

PIAFE PROGRAMMABLE ISDN AUDIO FRONT END

STMicroelectronics 

ST5080A

the 2nd control byte, data is loaded into the ap-

propriate programmable register. CS- must return

high at the end of the 2nd byte.

To read-back status information from PIAFE, the

first byte of the appropriate instruction is strobed

in during the first CS- pulse, as defined in Table

1. CS- must be set low for a further 8 CCLK cy-

cles, during which data is shifted out of the CO

pin on the falling edges of CCLK.

When CS- is high, CO pin is in the high imped-

ance Tri-state, enabling CO pins of several de-

vices to be multiplexed together.

Thus, to summarise, 2 byte READ and WRITE in-

structions may use either two 8-bit wide CS-

pulses or a single 16 bit wide CS- pulse.

Control channel access to PCM interface:

It is possible to access the B channel previously

selected in Register CR1.

A byte written into Control Register CR3 will be

automatically transmitted from DX output in the

following frame in place of the transmit PCM data.

A byte written into Control Register CR2 will be

automatically sent through the receive path to the

Receive amplifiers.

In order to implement a continuous data flow from

the Control MICROWIRE interface to a B chan-

nel, it is necessary to send the control byte on

each PCM frame.

A current byte received on DR input can be read

in the register CR2. In order to implement a con-

tinuous data flow from a B channel to MI-

CROWIRE interface, it is necessary to read regis-

ter CR2 at each PCM frame.

GCI COMPATIBLE MODE

GCI interface is an European standardized inter-

face to connect ISDN dedicated components in

the different configurations of equipment as Ter-

minals, Network Terminations, PBX, etc...

In a Terminal equipment, this interface called

SCIT for Special Circuit Interface for Terminals al-

lows for example connection between:

- ST5421 (SID-GCI) and ST5451 (HDLC/GCI

controller) used for 16 kbit/s D channel packet

frames processing and SID control,

- Peripheral devices connected to a 64 kbit/s B

channel and ST5451 used for GCI peripheral

control.

ST5080A may be assigned to one of the B chan-

nels present on the GCI interface and is moni-

tored via a control channel which is multiplexed

with the 64 kbit/s Voice Data channels.

Figure 2 shows the frame structure at the GCI in-

terface. Two 256 kbit/s channel are supported.

a)GCI channel 0: It is structured in four sub-

channels:

– B1 channel 8 bits per frame

10/32

– B2 channel 8 bits per frame

– M channel 8 bits per frame ignored by PIAFE

– SC channel 8 bits per frame ignored by

PIAFE

Only B1 or B2 channel can be selected in

PIAFE for PCM data transfer.

b)GCI channel 1: It is structured also in four

subchannels:

– B1* channel 8 bits per frame

– B2* channel 8 bits per frame

– M* channel 8 bits per frame

– SC* which is structured as follows:

6 bits ignored by PIAFE

A* bit associated with M* channel

E* bit associated with M* channel.

B1* or B2* channel can be selected in PIAFE

for PCM data transfer.

M* channel and two associated bits E* and A*

are used for PIAFE control.

Thus, to summarize, B1, B2, B1* or B2* channel

can be selected to transmit PCM data and M*

channel is used to read/write status/command pe-

ripheral device registers. Protocol for byte ex-

change on the M* channel uses E* and A* bits.

Physical Interface

The interface is physically constitued with 4 wires:

Input Data wire:

DR

Output Data wire:

DX

Bit Clock:

MCLK

Frame Synchronization: FS

Data is synchronized by MCLK and FS clock in-

puts.

FS insures reinitialization of time slot counter at

each frame beginning. The rising edge or FS is

the reference time for the first GCI channel bit.

Data is transmitted in both directions at half the

MCLK input frequency. Data is transmitted on the

the rising edge of MCLK and is sampled one pe-

riod after the transmit rising edge, also on a rising

edge.

Note: Transmit data may be sampled by far-end

device ie SID ST5421 on the falling edge 1.5 pe-

riod after the transmit rising edge.

Unused channel are high impedance. Data out-

puts are OPEN-DRAIN and need an external pull

up resistor.

COMBO activation/deactivation

ST5080A is automatically set in power down

mode when GCI clocks are idle. GCI section is re-

activated when GCI clocks are detected. PIAFE is

completly reactivated after receiving of a power

up command.

Exchange protocol on M* channel

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