ST5080 Просмотр технического описания (PDF) - STMicroelectronics
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ST5080 Datasheet PDF : 32 Pages
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Protocol allows a bidirectional transfer of bytes
between ST5080A and GCI controller with ac-
knowledgment at each received byte. For PIAFE,
standard protocol is simplified to provide read or
write register cycles almost identical to MI-
CROWIRE serial interface.
Write cycle
Control Unit sends through the GCI controller fol-
lowing bytes:
- First byte is the chip select byte. The first four
bits indicate the device address:
(A3,A2,A1,A0). The four last bits are ignored.
ST5080A compare the validated byte re-
ceived internally with the address defined by
pins A3, A2, A1, A0. If comparison is true,
byte is acknowledged, if not, ST5080A does
not acknowledge the byte.
NOTE: An internal ”message in progress” flag re-
mains active till the end of the complete message
transmission to avoid irrelevant acknowledgement
of any further byte.
- Second byte is structured as defined in Ta-
ble 1.
- Third byte is the Data byte to write into the
Register as indicated in Table 1.
It is possible but optional to write to several differ-
ent registers in a single message. In this case the
Chip Select byte is sent only once at the begin-
ning of the message, the device automatically
toggles between address byte and data byte.
Read cycle
Control Unit sends two bytes. First byte is the
chip select byte as defined above. Second byte is
structured as defined in Table 1.
If PIAFE identifies a read-back cycle, bit 2 of byte
1 in Table 1 equal 1, it has to respond to the Con-
trol Unit by sending a single byte message which
is the content of the addressed register.
It is possible but optional to request several differ-
ent read-back register cycles in a single message
but it is recommended to wait the answer before
requesting a new read back to avoid loss of data.
ST5080A responds by sending a single data byte
message at each request.
Received byte validation:
A received byte is validated if it is detected two
consecutive times identical.
Exchange Protocol:
Exchange protocol is identical for both directions.
Sender uses E* bit to indicate that it is sending a
M* byte while receiver uses A* bit to acknowledge
received byte.
When no message is transferred, E* bit and A* bit
ST5080A
are forced to inactive state.
A transmission is initialized by sender putting E*
bit from inactive state to active state and by send-
ing first byte on M* channel in the same frame.
Transmission of a message is allowed only if A*
bit from the receiver has been set inactive for at
least two frames.
When receiver is ready, it validates the received
byte internally when received in two consecutive
frames identical. Then the receiver sets first A* bit
from inactive to active state (pre-acknow-
legement), and maintains A* bit active at least in
the following frame (acknowledgement). If valida-
tion is not possible, (two last bytes received are
not identical), receiver aborts the message setting
A* bit active for only a single frame.
For the first byte received, Abort sequence is not
allowed. PIAFE does not respond either if two last
bytes are not identical or if the byte received does
not meet the Chip Select byte defined by A0-A3
pins bias.
A second byte may be transmitted by the sender
putting E* bit from active to inactive state and
sending the second byte on the M* channel in the
same frame. E* bit is set inactive for only one
frame. If it remains inactive more than one frame,
it is an end of message (i.e. not second byte
available).
The second byte may be transmitted only after re-
ceiving the pre-acknowledgment of the previous
byte transmitted (see Fig. 3). The same protocol
is used if a third byte is transmitted. Each byte
has to be transmitted at least in two consecutive
frames.
The receiver validates current received byte as
done on first byte and then set A* bit in the next
two frames first from active to inactive state (pre-
acknowledgement), and after from inactive to ac-
tive state (acknowledgement). If the receiver can-
not validate the received current byte (two bytes
received are not identical), it pre-acknowledges
normally, but let A* bit in the inactive state in the
next frame which indicates an abort request.
If a message sent by ST5080A is aborted, it will
stop the message and wait for a new read cycle
instruction from the controller.
A message received by ST5080A is acknow-
ledged or aborted without flow Control.
Figures 3 gives timing of a write cycle. Most sig-
nificant bit (MSB) of a Monitor byte is sent first on
M* channel.
E* and A* bits are active low and inactive state on
DOUT is high impedance.
PROGRAMMABLE FUNCTIONS
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