IDT723612L15PQF(1997) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723612L15PQF
(Rev.:1997)

BiCMOS SyncBiFIFO 64 x 36 x 2

Integrated Device Technology 

IDT723612 BiCMOS SyncBiFIFO™

64 x 36 x 2

CLKB

CSB

W/RB

MBB

ENB

tCLK

tCLKH

tCLKL

LOW

LOW

LOW

tENS2

tENH2

COMMERCIAL TEMPERATURE RANGE

EFB

B0 - B35

CLKA

FFA

HIGH

tA

Previous Word in FIFO1 Output Register

tSKEW1(1)

Next Word From FIFO1

tCLK

tCLKH

tCLKL

1

FIFO1 Full

2

tWFF

tWFF

CSA

LOW

WRA

MBA

HIGH

tENS3

tENH3

tENS2

tENH2

ENA

tDS

tDH

A0 - A35

To FIFO1

3136 drw 11

Note:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the

next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then FFA may

transition HIGH one CLKA cycle later than shown.

Figure 8. FFA Flag Timing and First Available Write when FIFO1 is Full.

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