IDT723612L15PQF(1997) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723612L15PQF
(Rev.:1997)

BiCMOS SyncBiFIFO 64 x 36 x 2

Integrated Device Technology 

IDT723612 BiCMOS SyncBiFIFO™

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

inputs. When data is read from a port with parity generation

selected, the lower eight bits of each byte are used to generate

a parity bit according to the level on the ODD/EVEN select.

The generated parity bits are substituted for the levels origi-

nally written to the most significant bits of each byte as the

word is read to the data outputs.

Parity bits for FIFO data are generated after the data is

read from SRAM and before the data is written to the output

register. Therefore, the port-A parity generate select (PGA)

and odd/even parity select (ODD/EVEN) have setup and hold

time constraints to the port-A clock (CLKA) and the port-B

parity generate select (PGB) and ODD/EVEN have setup and

hold-time constraints to the port-B clock (CLKB). These

timing constraints only apply for a rising clock edge used to

read a new word to the FIFO output register.

The circuit used to generate parity for the mail1 data is

shared by the port-B bus (B0-B35) to check parity and the

circuit used to generate parity for the mail2 data is shared by

the port-A bus (A0-A35) to check parity. The shared parity

trees of a port are used to generate parity bits for the data in

a mail register when the port write/read select (W/RA, W/RB)

input is LOW, the port mail select (MBA, MBB) input is HIGH,

chip select (CSA, CSB) is LOW, enable (ENA, ENB) is HIGH,

and port parity generate select (PGA, PGB) is HIGH. Gener-

ating parity for mail register data does not change the contents

of the register.

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