SN74LS161AML1 Просмотр технического описания (PDF) - ON Semiconductor
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SN74LS161AML1 Datasheet PDF : 6 Pages
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SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A
AC WAVEFORMS (continued)
COUNT ENABLE TRICKLE INPUT
TO TERMINAL COUNT OUTPUT DELAYS
The positive TC pulse occurs when the outputs are in the
(Q0 • Q1 • Q2 • Q3) state for the LS160 and LS162 and the
(Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163.
CET
TC
Figure 3
1.3 V
1.3 V
tPLH
1.3 V
tPHL
1.3 V
OTHER CONDITIONS: CP = PE = CEP = MR = H
CLOCK TO TERMINAL COUNT DELAYS
The positive TC pulse is coincident with the output state
(Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163 and
(Q0 • Q1 • Q2 • Q3) for the LS161 and LS163.
CP
TC
Figure 4
1.3 V
tPLH
1.3 V
1.3 V
1.3 V
tPHL
1.3 V
OTHER CONDITIONS: PE = CEP = CET = MR = H
SETUP TIME (ts) AND HOLD TIME (th)
FOR PARALLEL DATA INPUTS
The shaded areas indicate when the input is permitted to
change for predictable output performance.
CP
ts(H)
• • • P0 P1 P2 P3
• • • Q0 Q1 Q2 Q3
Figure 5
1.3 V
th(H) = 0
ts(L)
1.3 V
1.3 V
1.3 V
th(L) = 0
1.3 V
OTHER CONDITIONS: PE = L, MR = H
SETUP TIME (ts) AND HOLD TIME (th) FOR
COUNT ENABLE (CEP) AND (CET) AND
PARALLEL ENABLE (PE) INPUTS
The shaded areas indicate when the input is permitted to
change for predictable output performance.
CP
ts(L)
SR or PE
1.3 V
1.3 V
th (L) = 0
ts(H)
th(H) = 0
1.3 V
PARALLEL LOAD
(See Fig. 5)
1.3 V
COUNT MODE
(See Fig. 7)
Q RESPONSE TO PE
RESET
COUNT OR LOAD
Q RESPONSE TO SR
Figure 6
CP
ts(H)
CEP
ts(H)
CET 1.3 V
1.3 V
th(H) = 0
ts(L)
1.3 V
th(H) = 0
1.3 V
COUNT
1.3 V
th(L) = 0
1.3 V
ts(L)
HOLD
1.3 V
1.3 V
th(L) = 0
1.3 V
HOLD
Q
OTHER CONDITIONS: PE = H, MR = H
Figure 7
FAST AND LS TTL DATA
5-283
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