HC6094 Просмотр технического описания (PDF) - Intersil

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HC6094

ADSL Analog Front End Chip

Intersil 

HC6094

Shift Registers Format

REGISTER

RX Gain

TX Gain

A0

A1

A2

A3

D0 D1 D2 D3 D4 D5 D6 D7

1

0

X

X

PGA1 Gain

PGA2 Gain

0

0

X

X

PGA0 Gain

TX PGA0 GAIN

D2

D1

D0

GAIN IN dB

1

1

X

-12

1

0

1

-10

1

0

0

-8

0

1

1

-6

0

1

0

-4

0

0

1

-2

0

0

0

0

RX PGA1 GAIN

D3

D2

D1

D0

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

X

X

X

NOTE: PGA1 is an inverting amplifier.

GAIN IN dB

0

3

6

9

12

15

18

21

24

RX PGA2 GAIN

D7

D6

D5

D4

GAIN IN dB

0

0

0

0

-9

0

0

0

1

-6

0

0

1

0

-3

0

0

1

1

0

0

1

0

0

3

0

1

0

1

6

0

1

1

0

9

0

1

1

1

12

1

X

X

0

15

1

X

X

1

18

Filter Mask Template

AVERAGE

GP

PASSBAND

GAIN

-GP

GS

1.104 2.65

GM

9.94

FREQUENCY (MHz)

7

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