HC6094 Просмотр технического описания (PDF) - Intersil
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HC6094 Datasheet PDF : 9 Pages
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[ /Title
(HC60
94)
/Sub-
ject
(ADSL
Ana-
log
Front
End
Chip)
/Autho
r ()
/Key-
words
(Har-
ris
Semi-
con-
ductor,
Tele-
com,
SLICs,
SLACs
, Tele-
phone,
Tele-
phony,
WLL,
Wire-
less
Local
Loop,
PBX,
Pri-
vate
Branch
Exchan
ge,
NT1+,
CO,
Cen-
Semiconductor
February 1999
NO
Call
CRoeErnOCetrOBmaSMlaOAiMl:pLEpEcNlTeiDcnEaEtaPtDipoRpRnO@sEDP1hUL-aC8Ar0rTCi0sE-.4cM4o2Em-N7T747
HC6094
ADSL Analog Front End Chip
Features
• 14-Bit 5 MSPS DAC
• Programmable Gain Stages
• Anti-Aliasing and Reconstruction Filters
Applications
• FDM DMT ADSL
• CAP ADSL
• EC DMT ADSL
• Communications Receiver
Description
The HC6094 performs the Analog processing for the ADSL
chip set. The transmit chain has a 14 Bit DAC, a third-order
Chebyshev reconstruction filter and a programmable attenu-
ator (-12 to 0dB) capable of driving a 220Ω differential load.
The receiver chain has a high impedance input stage, pro-
grammable gain stage (0 to 24dB), additional programmable
gain (-9 to 18dB) and a third-order Chebyshev anti-aliasing
filter for driving an off-chip A/D.
Laser trimmable thin-film resistors are used to set the filter
cutoff frequency and DAC linearity. The transmit and receive
signal chains are specified at 65dB MTPR.
Ordering Information
PART
NUMBER
TEMP.
RANGE (oC)
PACKAGE
HC6094IN
-40 to 85 44 Ld MQFP
PKG. NO.
Q44.10x10
Pinout
HC6094
(MQFP)
TOP VIEW
44 43 42 41 40 39 38 37 36 35 34
D11
1
33
VSSA_ATT
D10
2
32
VDDA_TX
D9
3
31
VSSA_TX
D8
4
30
ARTN
D7
5
29
VDDD_RX
D6
6
28
CS
D5
7
27
SDI
D4
8
26
RST
D3
9
25
SCLK
D2
10
24
GNDD__RX
D1
11
23
12 13 14 15 16 17 18 19 20 21 22
GNDA_RX
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1999
1
File Number 4260.2
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