CS8405A-CZZ Просмотр технического описания (PDF) - Cirrus Logic

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CS8405A-CZZ

96 kHz Digital Audio Interface Transmitter

Cirrus Logic 

CS8405A

8.5 Serial Audio Input Port Data Format (05h)

7

SIMS

6

SISF

5

SIRES1

4

SIRES0

3

SIJUST

2

SIDEL

1

SISPOL

0

SILRPOL

SIMS - Master/Slave Mode Selector

Default = ‘0’

0 - Serial audio input port is in slave mode

1 - Serial audio input port is in master mode

SISF - ISCLK frequency (for master mode)

Default = ‘0’

0 - 64*Fs

1 - 128*Fs

SIRES1:0 - Resolution of the input data, for right-justified formats

Default = ‘00’

00 - 24-bit resolution

01 - 20-bit resolution

10 - 16-bit resolution

11 - Reserved

SIJUST - Justification of SDIN data relative to ILRCK

Default = ‘0’

0 - Left-justified

1 - Right-justified

SIDEL - Delay of SDIN data relative to ILRCK, for left-justified data formats

Default = ‘0’

0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge (left justified mode)

1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge (I²S mode)

SISPOL - ISCLK clock polarity

Default = ‘0’

0 - SDIN sampled on rising edges of ISCLK

1 - SDIN sampled on falling edges of ISCLK

SILRPOL - ILRCK clock polarity

Default = ‘0’

0 - SDIN data is for the left channel when ILRCK is high

1 - SDIN data is for the right channel when ILRCK is high

20

DS469F2

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