CS8427-IS Просмотр технического описания (PDF) - Cirrus Logic
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CS8427-IS Datasheet PDF : 59 Pages
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CS8427
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF)
Parameter
Symbol Min Typ Max Units
OSCLK Active Edge to SDOUT Output Valid
SDIN Setup Time Before ISCLK Active Edge
SDIN Hold Time After ISCLK Active Edge
Master Mode
(Note 8) tdpd
(Note 8)
tds
(Note 8)
tdh
-
-
20
ns
20
-
-
ns
20
-
-
ns
O/RMCK to I/OSCLK active edge delay
O/RMCK to I/OLRCK delay
I/OSCLK and I/OLRCK Duty Cycle
(Note 8, 9) tsmd
(Note 10) tlmd
0
-
10
ns
0
-
10
ns
-
50
-
%
Slave Mode
I/OSCLK Period
(Note 11) tsckw
36
-
-
ns
I/OSCLK Input Low Width
tsckl
14
-
-
ns
I/OSCLK Input High Width
tsckh
14
-
-
ns
I/OSCLK Active Edge to I/OLRCK Edge
tlrckd
20
-
-
ns
(Note 8, 10, 12)
I/OLRCK Edge Setup Before I/OSCLK Active Edge
tlrcks
20
-
-
ns
(Note 8, 10, 13)
Notes: 8. The active edges of ISCLK and OSCLK are programmable.
9. When OSCLK, OLRCK, ISCLK, and ILRCK are derived from OMCK they are clocked from its rising
edge. When these signals are derived from RMCK, they are clocked from its falling edge.
10. The polarity of ILRCK and OLRCK is programmable.
11. No more than 128 SCLK per frame.
12. This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK
has changed.
13. This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has
changed.
IS C L K
OSCLK
(output)
IL R C K
OLRCK
(output)
t smd
RMCK
(output)
Hardware M ode
t lm d
ILRCK
OLRCK
(input)
t lrckd
ISCLK
OSCLK
(input)
t lrcks
t sckh
tsckl
t sckw
SDIN
RMCK
(output)
OMCK
(in p u t)
Software M ode
SDOUT
tds tdh
tdpd
Figure 1. Audio Port Master Mode Timing
Figure 2. Audio Port Slave Mode and Data Input Timing
8
DS477F1
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