CS8427-IS Просмотр технического описания (PDF) - Cirrus Logic

Номер в каталоге

Компоненты Описание

Список матч

CS8427-IS

96 kHz Digital Audio Interface Transceiver

Cirrus Logic 

CS8427

Figure 6. CS8427 Internal Block Diagram..................................................................................... 13

Figure 7. Software Mode Audio Data Flow Switching Options...................................................... 19

Figure 8. CS8427 Clock Routing................................................................................................... 20

Figure 9. AES3 Input to Serial Audio Output, Serial Audio Input to AES3 Out ............................. 21

Figure 11. Input Serial Port to AES3 Transmitter without PLL ...................................................... 21

Figure 10. AES3 Input to Serial Audio Output Only ...................................................................... 21

Figure 12. Input Serial Port to AES3 Transmitter with PLL ........................................................... 21

Figure 13. AES3 Receiver Timing for U pin output data ............................................................... 22

Figure 14. AES3 Transmitter Timing for C, U and V pin input data............................................... 22

Figure 15. Serial Audio Input Example Formats............................................................................ 23

Figure 16. Serial Audio Output Example Formats......................................................................... 24

Figure 17. Control Port Timing in SPI Mode.................................................................................. 26

Figure 18. Control Port Timing in I²C Mode................................................................................... 26

Figure 19. Hardware Mode............................................................................................................ 42

Figure 20. Professional Output Circuit .......................................................................................... 49

Figure 21. Consumer Output Circuit.............................................................................................. 49

Figure 22. TTL/CMOS Output Circuit ............................................................................................ 49

Figure 23. Professional Input Circuit ............................................................................................. 50

Figure 24. Transformerless Professional Input Circuit .................................................................. 50

Figure 25. Consumer Input Circuit ................................................................................................ 50

Figure 26. TTL/CMOS Input Circuit............................................................................................... 50

Figure 27. Channel Status Data Buffer Structure.......................................................................... 51

Figure 28. Flowchart for Reading the E Buffer .............................................................................. 52

Figure 29. Flowchart for Writing the E Buffer ................................................................................ 52

Figure 30. PLL Block Diagram ...................................................................................................... 54

Figure 31. Recommended Layout Example .................................................................................. 55

Figure 32. Jitter Tolerance Template ............................................................................................ 57

Figure 33. Revision A .................................................................................................................... 58

Figure 34. Revision A1 .................................................................................................................. 58

Figure 35. Revision A2 using A1 values........................................................................................ 58

Figure 36. Revision A2 using A2* values ...................................................................................... 58

LIST OF TABLES

Table 1. Control Register Map Summary ...................................................................................... 27

Table 2. Hardware Mode Start-up Options.................................................................................... 43

Table 3. Serial Audio Output Formats Available in Hardware Mode ............................................. 43

Table 4. Serial Audio Input Formats Available in Hardware Mode................................................ 43

Table 5. Second Line Part Marking ............................................................................................... 56

Table 6. Locking to RXP/RXN - Fs = 8 to 96 kHz ......................................................................... 56

Table 7. Locking to RXP/RXN - Fs = 32 to 96 kHz ....................................................................... 56

Table 8. Locking to the ILRCK Input ............................................................................................. 57

Table 9. Revision History .............................................................................................................. 59

4

DS477F1

Share Link: