HD64F7065SF Просмотр технического описания (PDF) - Renesas Electronics

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HD64F7065SF

Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7000 Series

Renesas Electronics 

13.2.2 Timer Control/Status Register (TCSR) ................................................................ 508

13.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 510

13.2.4 Notes on Register Access..................................................................................... 511

13.3 Operation........................................................................................................................... 513

13.3.1 Operation in Watchdog Timer Mode ................................................................... 513

13.3.2 Operation in Interval Timer Mode ....................................................................... 515

13.3.3 Operation When Clearing Software Standby Mode ............................................. 515

Section 14 Serial Communication Interface (SCI)..................................................... 517

14.1 Overview........................................................................................................................... 517

14.1.1 Features................................................................................................................ 517

14.1.2 Block Diagrams.................................................................................................... 519

14.1.3 Pin Configuration................................................................................................. 520

14.1.4 Register Configuration ......................................................................................... 521

14.2 Register Descriptions ........................................................................................................ 522

14.2.1 Receive Shift Register (SCRSR) .......................................................................... 522

14.2.2 Receive FIFO Data Register (SCFRDR).............................................................. 523

14.2.3 Transmit Shift Register (SCTSR)......................................................................... 523

14.2.4 Transmit FIFO Data Register (SCFTDR) ............................................................ 524

14.2.5 Serial Mode Register (SCSMR)........................................................................... 524

14.2.6 Serial Control Register (SCSCR) ......................................................................... 527

14.2.7 Serial Status 1 Register (SC1SSR)....................................................................... 532

14.2.8 Serial Status 2 Register (SC2SSR)....................................................................... 537

14.2.9 Bit Rate Register (SCBRR).................................................................................. 540

14.2.10 FIFO Control Register (SCFCR).......................................................................... 549

14.2.11 FIFO Data Count Register (SCFDR) ................................................................... 551

14.2.12 FIFO Error Register (SCFER) ............................................................................. 552

14.2.13 IrDA Mode Register (SCIMR)............................................................................. 553

14.3 Operation........................................................................................................................... 554

14.3.1 Overview.............................................................................................................. 554

14.3.2 Operation in Asynchronous Mode ....................................................................... 557

14.3.3 Multiprocessor Communication Function ............................................................ 568

14.3.4 Operation in Synchronous Mode.......................................................................... 577

14.3.5 Use of Transmit/Receive FIFO Buffers ............................................................... 587

14.3.6 Operation in IrDA Mode...................................................................................... 590

14.4 SCI Interrupt Sources and the DMAC............................................................................... 593

14.5 Usage Notes ...................................................................................................................... 594

Section 15 A/D Converter................................................................................................. 601

15.1 Overview........................................................................................................................... 601

15.1.1 Features................................................................................................................ 601

Rev. 5.00 Sep 11, 2006 page xvii of xxii

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