HD64F7065SF Просмотр технического описания (PDF) - Renesas Electronics
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HD64F7065SF
Renesas Electronics
HD64F7065SF Datasheet PDF : 941 Pages
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10.3 Interface to Bus Master ..................................................................................................... 406
10.3.1 16-Bit Registers ................................................................................................... 406
10.3.2 8-Bit Registers ..................................................................................................... 406
10.4 Operation........................................................................................................................... 408
10.4.1 Overview.............................................................................................................. 408
10.4.2 Basic Functions .................................................................................................... 409
10.4.3 Synchronous Operation........................................................................................ 414
10.4.4 Buffer Operation .................................................................................................. 417
10.4.5 Cascaded Operation ............................................................................................. 421
10.4.6 PWM Modes ........................................................................................................ 422
10.4.7 Phase Counting Mode .......................................................................................... 427
10.5 Interrupts ........................................................................................................................... 434
10.5.1 Interrupt Sources and Priorities............................................................................ 434
10.5.2 DMAC Activation................................................................................................ 436
10.5.3 A/D Converter Activation .................................................................................... 436
10.6 Operation Timing .............................................................................................................. 437
10.6.1 Input/Output Timing ............................................................................................ 437
10.6.2 Interrupt Signal Timing........................................................................................ 441
10.7 Usage Notes ...................................................................................................................... 445
Section 11 Motor Management Timer (MMT)........................................................... 455
11.1 Overview........................................................................................................................... 455
11.1.1 Features................................................................................................................ 455
11.1.2 Block Diagram ..................................................................................................... 456
11.1.3 Pin Configuration................................................................................................. 457
11.1.4 Register Configuration ......................................................................................... 457
11.2 Register Descriptions ........................................................................................................ 459
11.2.1 Timer Mode Register (TMDR) ............................................................................ 459
11.2.2 Timer Control Register (TCNR) .......................................................................... 460
11.2.3 Timer Status Register (TSR) ................................................................................ 462
11.2.4 Timer Counter (TCNT)........................................................................................ 463
11.2.5 Timer Buffer Registers (TBR) ............................................................................. 463
11.2.6 Timer General Registers (TGR)........................................................................... 464
11.2.7 Timer Dead Time Counters (TDCNT)................................................................. 464
11.2.8 Timer Dead Time Data Register (TDDR)............................................................ 465
11.2.9 Timer Period Buffer Register (TPBR) ................................................................. 465
11.2.10 Timer Period Data Register (TPDR).................................................................... 466
11.3 Operation........................................................................................................................... 466
11.3.1 Sample Setting Procedure .................................................................................... 467
11.3.2 Overview of Operation......................................................................................... 468
11.3.3 Output Protection Functions ................................................................................ 476
Rev. 5.00 Sep 11, 2006 page xv of xxii
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