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SC68C562

CMOS dual universal serial communications controller (CDUSCC)

Philips Electronics 

Philips Semiconductors

CMOS Dual universal serial communications controller

(CDUSCC)

Product specification

SC68C562

• 1X or 16X Rx and Tx clock factors

• Parity, overrun, and framing error detection

• False start bit detection

• Start bit search 1/2-bit time after framing error detection

• Break generation with handshake for counting break characters

• Detection of start and end of received break

• Character compare with optional interrupt on match

• Transmits up to 10Mb/s at 1X and receive up to 1Mb/s at 16X

data rates

Character-Oriented Protocol Features

• Character length: 5 to 8 bits

• Odd or even parity, no parity, or force parity

• LRC or CRC generation and checking

• Optional opening PAD transmission

• One or two SYN characters

• External sync capability

• SYN detection and optional stripping

• SYN or MARK line fill on underrun

• Idle in MARK or SYNs

• Parity, FCS, overrun, and underrun error detection

BISYNC Features

• EBCDIC or ASCII header, text and control messages

• SYN, DLE stripping

• EOM (end of message) detection and transmission

• Auto transparent mode switching

• Auto hunt after receipt of EOM sequence (with closing PAD check

after EOT or NAK)

• Control character sequence detection for both transparent and

normal text

Bit-Oriented Protocol Features

• Character length: 5 to 8 bits

• Detection and transmission of residual character: 0–7 bits

• Automatic switch to programmed character length for I field

• Zero insertion and deletion

• Optional opening PAD transmission

• Detection and generation of FLAG, ABORT, and IDLE bit patterns

• Detection and generation of shared (single) FLAG between

frames

• Detection of overlapping (shared zero) FLAGs

• ABORT, ABORT-FLAGs, or FCS FLAGs line fill on underrun

• Idle in MARK or FLAGs

• Secondary address recognition including group and global

address

• Single- or dual-octet secondary address

• Extended address and control fields

• Short frame rejection for receiver

• Detection and notification of received end of message

• CRC generation and checking

• SDLC loop mode capability

ORDERING INFORMATION

DESCRIPTION

48-Pin Plastic Dual In-Line Package (DIP)

52-Pin Plastic Leaded Chip Carrier (PLCC) Package

VCC = +5V ±10%,

TA = 0 to +70°C

Serial Data Rate =

10Mbps Maximum

SC68C562C1N

SC68C562C1A

VCC = +5V ±10%,

TA = –40 to +85°C

Serial Data Rate =

8Mbps Maximum

Not available

SC68C562A8A

DWG #

SOT240-1

SOT238-3

ABSOLUTE MAXIMUM RATINGS1

SYMBOL

TA

TSTG

VCC

VS

PARAMETER

Operating ambient temperature2

Storage temperature

Voltage from VCC to GND3

Voltage from any pin to ground3

COMMERCIAL

0 to +70

-65 to +150

–0.5 to +7.0

–0.5 to VCC +0.5

RATING

INDUSTRIAL

-40 to +85

-65 to +150

–0.5 to +7.0

–0.5 to VCC +0.5

UNIT

°C

°C

V

V

1998 Sep 04

3

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