Q67100-H6440 Просмотр технического описания (PDF) - Infineon Technologies

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Q67100-H6440

ICs for Communications

Infineon Technologies 

SAB 82538

SAF 82538

Pin Definitions and Function (cont’d)

Pin No. Symbol

Input (I)

Function

Output (O)

81

RES

I

Reset

A high signal on this pin forces the ESCC8 into

reset state. During Reset the ESCC8 is in power

up mode, after Reset in power down mode. Re-

activation of each channel is done via bit

CCR0.PU (refer to chapter 3.2).

During Reset

– all uni-directional output stages are in high-

impedance state,

– all bi-directional output stages (data bus)

are in high-impedance state if signals RD

and INTA are “high”,

– “output” XTAL2 is in high-impedance if input

XTAL1 is “high” (the internal oscillator is

disabled during reset)

93

BHE/BLE I

Bus High Enable (Siemens/Intel bus mode)

If 16-bit bus interface mode is enabled, this signal

indicates a data transfer on the upper byte of the

data bus (D8 … D15). In 8-bit bus interface mode

this signal has no function and should be tied to

VDD. Refer to chapter 2.2.1 for detailed

information.

Bus Low Enable (Motorola bus mode)

If 16-bit bus interface mode is enabled, this signal

indicates a data transfer on the lower byte of the

data bus (D0 … D7). In 8-bit bus interface mode

this signal has no function and should be tied to

VDD. Refer to chapter 2.2.1 for detailed

information.

82

WIDTH I

Width Of Bus Interface (Bus Interface Mode)

A low signal on this input selects the 8-bit bus

interface mode. A high signal on this input selects

the 16-bit bus interface mode. In this case word

transfer to/from the internal registers is enabled.

Byte transfers are implemented by using A0 and

BHE/BLE.

Semiconductor Group

13

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