Q67100-H6440 Просмотр технического описания (PDF) - Infineon Technologies

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Q67100-H6440

ICs for Communications

Infineon Technologies 

SAB 82538

SAF 82538

Pin Definitions and Function (cont’d)

Pin No. Symbol

Input (I)

Function

Output (O)

95

RD/DS I

Read Enable (Siemens/Intel bus mode)

This signal indicates a read operation. When the

ESCC8 is selected via CS the RD signal enables

the bus drivers to output data from an internal

register addressed via A0 … A8 on to Data Bus.

For more information about control/status register

and FIFO access in the different bus interface

modes refer to chapter 2.

If DMA transfer is selected via DACKx, the RD

signal enables the bus drivers to put data from the

corresponding Receive FIFO on the Data Bus.

Inputs A1 … A8 are ignored. A0 and BHE/BLE

are used to select byte or word access.

Data Strobe (Motorola bus mode)

This pin serves as input to control read/write

operations.

96

WR/R/W I

Write Enable (Siemens/Intel bus mode)

This signal indicates a write operation. When CS

is active the ESCC8 loads an internal register with

data provided via the Data Bus. For more

information about control/status register and

FIFO access in the different bus interface modes

refer to chapter 2.

If DMA transfer is selected via DACKx the WR

signal enables latching data from the Data Bus on

the top of the corresponding Transmit FIFO.

Inputs A0 … A8 are ignored.

Read/Write Enable (Motorola bus mode)

This signal distinguishes between read and write

operation.

94

CS

I

Chip Select

A low signal selects the ESCC8 for read/write

operations. CS has no function in interrupt

acknowledge or DMA cycles.

Semiconductor Group

12

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